Struct lpc55_pac::syscon::sdioclkctrl::W

pub struct W(_);

Register SDIOCLKCTRL writer

Implementations

impl W

pub fn cclk_drv_phase(&mut self) -> CCLK_DRV_PHASE_W<'_>

Bits 0:1 - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.

pub fn cclk_sample_phase(&mut self) -> CCLK_SAMPLE_PHASE_W<'_>

Bits 2:3 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn phase_active(&mut self) -> PHASE_ACTIVE_W<'_>

Bit 7 - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.

pub fn cclk_drv_delay(&mut self) -> CCLK_DRV_DELAY_W<'_>

Bits 16:20 - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.

pub fn cclk_drv_delay_active(&mut self) -> CCLK_DRV_DELAY_ACTIVE_W<'_>

Bit 23 - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.

pub fn cclk_sample_delay(&mut self) -> CCLK_SAMPLE_DELAY_W<'_>

Bits 24:28 - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

pub fn cclk_sample_delay_active(&mut self) -> CCLK_SAMPLE_DELAY_ACTIVE_W<'_>

Bit 31 - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SDIOCLKCTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<SDIOCLKCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SDIOCLKCTRL_SPEC>> for W

fn from(writer: W<SDIOCLKCTRL_SPEC>) -> Self

Performs the conversion.