Module lpc55_pac::syscon::sdioclkctrl
source · [−]Expand description
SDIO CCLKIN phase and delay control
Structs
Field CCLK_DRV_DELAY_ACTIVE
reader - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
Field CCLK_DRV_DELAY_ACTIVE
writer - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
Field CCLK_DRV_DELAY
reader - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
Field CCLK_DRV_DELAY
writer - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in.
Field CCLK_DRV_PHASE
reader - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
Field CCLK_DRV_PHASE
writer - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
Field CCLK_SAMPLE_DELAY_ACTIVE
reader - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
Field CCLK_SAMPLE_DELAY_ACTIVE
writer - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
Field CCLK_SAMPLE_DELAY
reader - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Field CCLK_SAMPLE_DELAY
writer - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Field CCLK_SAMPLE_PHASE
reader - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Field CCLK_SAMPLE_PHASE
writer - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Field PHASE_ACTIVE
reader - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
Field PHASE_ACTIVE
writer - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.
Register SDIOCLKCTRL
reader
SDIO CCLKIN phase and delay control
Register SDIOCLKCTRL
writer
Enums
Enables drive delay, as controlled by the CCLK_DRV_DELAY field.
Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.
Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.
Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.