RegisterBlock

lpc55_pac::sdif

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 32 fields
    pub ctrl: Reg<CTRL_SPEC>,
    pub pwren: Reg<PWREN_SPEC>,
    pub clkdiv: Reg<CLKDIV_SPEC>,
    pub clkena: Reg<CLKENA_SPEC>,
    pub tmout: Reg<TMOUT_SPEC>,
    pub ctype: Reg<CTYPE_SPEC>,
    pub blksiz: Reg<BLKSIZ_SPEC>,
    pub bytcnt: Reg<BYTCNT_SPEC>,
    pub intmask: Reg<INTMASK_SPEC>,
    pub cmdarg: Reg<CMDARG_SPEC>,
    pub cmd: Reg<CMD_SPEC>,
    pub resp: [Reg<RESP_SPEC>; 4],
    pub mintsts: Reg<MINTSTS_SPEC>,
    pub rintsts: Reg<RINTSTS_SPEC>,
    pub status: Reg<STATUS_SPEC>,
    pub fifoth: Reg<FIFOTH_SPEC>,
    pub cdetect: Reg<CDETECT_SPEC>,
    pub wrtprt: Reg<WRTPRT_SPEC>,
    pub tcbcnt: Reg<TCBCNT_SPEC>,
    pub tbbcnt: Reg<TBBCNT_SPEC>,
    pub debnce: Reg<DEBNCE_SPEC>,
    pub rst_n: Reg<RST_N_SPEC>,
    pub bmod: Reg<BMOD_SPEC>,
    pub pldmnd: Reg<PLDMND_SPEC>,
    pub dbaddr: Reg<DBADDR_SPEC>,
    pub idsts: Reg<IDSTS_SPEC>,
    pub idinten: Reg<IDINTEN_SPEC>,
    pub dscaddr: Reg<DSCADDR_SPEC>,
    pub bufaddr: Reg<BUFADDR_SPEC>,
    pub cardthrctl: Reg<CARDTHRCTL_SPEC>,
    pub backendpwr: Reg<BACKENDPWR_SPEC>,
    pub fifo: [Reg<FIFO_SPEC>; 64],
    /* private fields */

}
Expand description

Register block

Fields§

§ctrl: Reg<CTRL_SPEC>

0x00 - Control register

§pwren: Reg<PWREN_SPEC>

0x04 - Power Enable register

§clkdiv: Reg<CLKDIV_SPEC>

0x08 - Clock Divider register

§clkena: Reg<CLKENA_SPEC>

0x10 - Clock Enable register

§tmout: Reg<TMOUT_SPEC>

0x14 - Time-out register

§ctype: Reg<CTYPE_SPEC>

0x18 - Card Type register

§blksiz: Reg<BLKSIZ_SPEC>

0x1c - Block Size register

§bytcnt: Reg<BYTCNT_SPEC>

0x20 - Byte Count register

§intmask: Reg<INTMASK_SPEC>

0x24 - Interrupt Mask register

§cmdarg: Reg<CMDARG_SPEC>

0x28 - Command Argument register

§cmd: Reg<CMD_SPEC>

0x2c - Command register

§resp: [Reg<RESP_SPEC>; 4]

0x30..0x40 - Response register

§mintsts: Reg<MINTSTS_SPEC>

0x40 - Masked Interrupt Status register

§rintsts: Reg<RINTSTS_SPEC>

0x44 - Raw Interrupt Status register

§status: Reg<STATUS_SPEC>

0x48 - Status register

§fifoth: Reg<FIFOTH_SPEC>

0x4c - FIFO Threshold Watermark register

§cdetect: Reg<CDETECT_SPEC>

0x50 - Card Detect register

§wrtprt: Reg<WRTPRT_SPEC>

0x54 - Write Protect register

§tcbcnt: Reg<TCBCNT_SPEC>

0x5c - Transferred CIU Card Byte Count register

§tbbcnt: Reg<TBBCNT_SPEC>

0x60 - Transferred Host to BIU-FIFO Byte Count register

§debnce: Reg<DEBNCE_SPEC>

0x64 - Debounce Count register

§rst_n: Reg<RST_N_SPEC>

0x78 - Hardware Reset

§bmod: Reg<BMOD_SPEC>

0x80 - Bus Mode register

§pldmnd: Reg<PLDMND_SPEC>

0x84 - Poll Demand register

§dbaddr: Reg<DBADDR_SPEC>

0x88 - Descriptor List Base Address register

§idsts: Reg<IDSTS_SPEC>

0x8c - Internal DMAC Status register

§idinten: Reg<IDINTEN_SPEC>

0x90 - Internal DMAC Interrupt Enable register

§dscaddr: Reg<DSCADDR_SPEC>

0x94 - Current Host Descriptor Address register

§bufaddr: Reg<BUFADDR_SPEC>

0x98 - Current Buffer Descriptor Address register

§cardthrctl: Reg<CARDTHRCTL_SPEC>

0x100 - Card Threshold Control

§backendpwr: Reg<BACKENDPWR_SPEC>

0x104 - Power control

§fifo: [Reg<FIFO_SPEC>; 64]

0x200..0x300 - SDIF FIFO

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