RegisterBlock

lpc55_pac::inputmux

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 26 fields
    pub sct0_inmux: [Reg<SCT0_INMUX_SPEC>; 7],
    pub timer0captsel: [Reg<TIMER0CAPTSEL_SPEC>; 4],
    pub timer1captsel: [Reg<TIMER1CAPTSEL_SPEC>; 4],
    pub timer2captsel: [Reg<TIMER2CAPTSEL_SPEC>; 4],
    pub pintsel: [Reg<PINTSEL_SPEC>; 8],
    pub dma0_itrig_inmux: [Reg<DMA0_ITRIG_INMUX_SPEC>; 23],
    pub dma0_otrig_inmux: [Reg<DMA0_OTRIG_INMUX_SPEC>; 4],
    pub freqmeas_ref: Reg<FREQMEAS_REF_SPEC>,
    pub freqmeas_target: Reg<FREQMEAS_TARGET_SPEC>,
    pub timer3captsel: [Reg<TIMER3CAPTSEL_SPEC>; 4],
    pub timer4captsel: [Reg<TIMER4CAPTSEL_SPEC>; 4],
    pub pintsecsel: [Reg<PINTSECSEL_SPEC>; 2],
    pub dma1_itrig_inmux: [Reg<DMA1_ITRIG_INMUX_SPEC>; 10],
    pub dma1_otrig_inmux: [Reg<DMA1_OTRIG_INMUX_SPEC>; 4],
    pub dma0_req_ena: Reg<DMA0_REQ_ENA_SPEC>,
    pub dma0_req_ena_set: Reg<DMA0_REQ_ENA_SET_SPEC>,
    pub dma0_req_ena_clr: Reg<DMA0_REQ_ENA_CLR_SPEC>,
    pub dma1_req_ena: Reg<DMA1_REQ_ENA_SPEC>,
    pub dma1_req_ena_set: Reg<DMA1_REQ_ENA_SET_SPEC>,
    pub dma1_req_ena_clr: Reg<DMA1_REQ_ENA_CLR_SPEC>,
    pub dma0_itrig_ena: Reg<DMA0_ITRIG_ENA_SPEC>,
    pub dma0_itrig_ena_set: Reg<DMA0_ITRIG_ENA_SET_SPEC>,
    pub dma0_itrig_ena_clr: Reg<DMA0_ITRIG_ENA_CLR_SPEC>,
    pub dma1_itrig_ena: Reg<DMA1_ITRIG_ENA_SPEC>,
    pub dma1_itrig_ena_set: Reg<DMA1_ITRIG_ENA_SET_SPEC>,
    pub dma1_itrig_ena_clr: Reg<DMA1_ITRIG_ENA_CLR_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§sct0_inmux: [Reg<SCT0_INMUX_SPEC>; 7]

0x00..0x1c - Input mux register for SCT0 input

§timer0captsel: [Reg<TIMER0CAPTSEL_SPEC>; 4]

0x20..0x30 - Capture select registers for TIMER0 inputs

§timer1captsel: [Reg<TIMER1CAPTSEL_SPEC>; 4]

0x40..0x50 - Capture select registers for TIMER1 inputs

§timer2captsel: [Reg<TIMER2CAPTSEL_SPEC>; 4]

0x60..0x70 - Capture select registers for TIMER2 inputs

§pintsel: [Reg<PINTSEL_SPEC>; 8]

0xc0..0xe0 - Pin interrupt select register

§dma0_itrig_inmux: [Reg<DMA0_ITRIG_INMUX_SPEC>; 23]

0xe0..0x13c - Trigger select register for DMA0 channel

§dma0_otrig_inmux: [Reg<DMA0_OTRIG_INMUX_SPEC>; 4]

0x160..0x170 - DMA0 output trigger selection to become DMA0 trigger

§freqmeas_ref: Reg<FREQMEAS_REF_SPEC>

0x180 - Selection for frequency measurement reference clock

§freqmeas_target: Reg<FREQMEAS_TARGET_SPEC>

0x184 - Selection for frequency measurement target clock

§timer3captsel: [Reg<TIMER3CAPTSEL_SPEC>; 4]

0x1a0..0x1b0 - Capture select registers for TIMER3 inputs

§timer4captsel: [Reg<TIMER4CAPTSEL_SPEC>; 4]

0x1c0..0x1d0 - Capture select registers for TIMER4 inputs

§pintsecsel: [Reg<PINTSECSEL_SPEC>; 2]

0x1e0..0x1e8 - Pin interrupt secure select register

§dma1_itrig_inmux: [Reg<DMA1_ITRIG_INMUX_SPEC>; 10]

0x200..0x228 - Trigger select register for DMA1 channel

§dma1_otrig_inmux: [Reg<DMA1_OTRIG_INMUX_SPEC>; 4]

0x240..0x250 - DMA1 output trigger selection to become DMA1 trigger

§dma0_req_ena: Reg<DMA0_REQ_ENA_SPEC>

0x740 - Enable DMA0 requests

§dma0_req_ena_set: Reg<DMA0_REQ_ENA_SET_SPEC>

0x748 - Set one or several bits in DMA0_REQ_ENA register

§dma0_req_ena_clr: Reg<DMA0_REQ_ENA_CLR_SPEC>

0x750 - Clear one or several bits in DMA0_REQ_ENA register

§dma1_req_ena: Reg<DMA1_REQ_ENA_SPEC>

0x760 - Enable DMA1 requests

§dma1_req_ena_set: Reg<DMA1_REQ_ENA_SET_SPEC>

0x768 - Set one or several bits in DMA1_REQ_ENA register

§dma1_req_ena_clr: Reg<DMA1_REQ_ENA_CLR_SPEC>

0x770 - Clear one or several bits in DMA1_REQ_ENA register

§dma0_itrig_ena: Reg<DMA0_ITRIG_ENA_SPEC>

0x780 - Enable DMA0 triggers

§dma0_itrig_ena_set: Reg<DMA0_ITRIG_ENA_SET_SPEC>

0x788 - Set one or several bits in DMA0_ITRIG_ENA register

§dma0_itrig_ena_clr: Reg<DMA0_ITRIG_ENA_CLR_SPEC>

0x790 - Clear one or several bits in DMA0_ITRIG_ENA register

§dma1_itrig_ena: Reg<DMA1_ITRIG_ENA_SPEC>

0x7a0 - Enable DMA1 triggers

§dma1_itrig_ena_set: Reg<DMA1_ITRIG_ENA_SET_SPEC>

0x7a8 - Set one or several bits in DMA1_ITRIG_ENA register

§dma1_itrig_ena_clr: Reg<DMA1_ITRIG_ENA_CLR_SPEC>

0x7b0 - Clear one or several bits in DMA1_ITRIG_ENA register

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