Struct lpc55_pac::i2s0::fifocfg::W

pub struct W(_);

Register FIFOCFG writer

Implementations

impl W

pub fn enabletx(&mut self) -> ENABLETX_W<'_>

Bit 0 - Enable the transmit FIFO.

pub fn enablerx(&mut self) -> ENABLERX_W<'_>

Bit 1 - Enable the receive FIFO.

pub fn txi2se0(&mut self) -> TXI2SE0_W<'_>

Bit 2 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.

pub fn pack48(&mut self) -> PACK48_W<'_>

Bit 3 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.

pub fn dmatx(&mut self) -> DMATX_W<'_>

Bit 12 - DMA configuration for transmit.

pub fn dmarx(&mut self) -> DMARX_W<'_>

Bit 13 - DMA configuration for receive.

pub fn waketx(&mut self) -> WAKETX_W<'_>

Bit 14 - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn wakerx(&mut self) -> WAKERX_W<'_>

Bit 15 - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.

pub fn emptytx(&mut self) -> EMPTYTX_W<'_>

Bit 16 - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.

pub fn emptyrx(&mut self) -> EMPTYRX_W<'_>

Bit 17 - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<FIFOCFG_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Trait Implementations

impl Deref for W

type Target = W<FIFOCFG_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<FIFOCFG_SPEC>> for W

fn from(writer: W<FIFOCFG_SPEC>) -> Self

Performs the conversion.