Struct lpc55_pac::syscon::sdioclkctrl::CCLK_SAMPLE_PHASE_W [−][src]
pub struct CCLK_SAMPLE_PHASE_W<'a> { /* fields omitted */ }
Field CCLK_SAMPLE_PHASE
writer - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.
Implementations
impl<'a> CCLK_SAMPLE_PHASE_W<'a>
[src]
impl<'a> CCLK_SAMPLE_PHASE_W<'a>
[src]pub fn variant(self, variant: CCLK_SAMPLE_PHASE_A) -> &'a mut W
[src]
Writes variant
to the field
pub fn enum_0_deg(self) -> &'a mut W
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0 degree shift.
pub fn enum_90_deg(self) -> &'a mut W
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90 degree shift.
pub fn enum_180_deg(self) -> &'a mut W
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180 degree shift.
pub fn enum_270_deg(self) -> &'a mut W
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270 degree shift.
pub fn bits(self, value: u8) -> &'a mut W
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Writes raw bits to the field
Auto Trait Implementations
impl<'a> Send for CCLK_SAMPLE_PHASE_W<'a>
impl<'a> Send for CCLK_SAMPLE_PHASE_W<'a>
impl<'a> Sync for CCLK_SAMPLE_PHASE_W<'a>
impl<'a> Sync for CCLK_SAMPLE_PHASE_W<'a>
impl<'a> Unpin for CCLK_SAMPLE_PHASE_W<'a>
impl<'a> Unpin for CCLK_SAMPLE_PHASE_W<'a>