Struct lpc55_pac::syscon::sdioclkctrl::CCLK_SAMPLE_PHASE_R

pub struct CCLK_SAMPLE_PHASE_R(_);

Field CCLK_SAMPLE_PHASE reader - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.

Implementations

impl CCLK_SAMPLE_PHASE_R

pub fn variant(&self) -> CCLK_SAMPLE_PHASE_A

Get enumerated values variant

pub fn is_enum_0_deg(&self) -> bool

Checks if the value of the field is ENUM_0_DEG

pub fn is_enum_90_deg(&self) -> bool

Checks if the value of the field is ENUM_90_DEG

pub fn is_enum_180_deg(&self) -> bool

Checks if the value of the field is ENUM_180_DEG

pub fn is_enum_270_deg(&self) -> bool

Checks if the value of the field is ENUM_270_DEG

Methods from Deref<Target = FieldReader<u8, CCLK_SAMPLE_PHASE_A>>

pub fn bits(&self) -> U

Reads raw bits from field.

pub fn bit(&self) -> bool

Value of the field as raw bits.

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0).

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1).

Trait Implementations

impl Deref for CCLK_SAMPLE_PHASE_R

type Target = FieldReader<u8, CCLK_SAMPLE_PHASE_A>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.