Enum lpc55_pac::syscon::sdioclkctrl::CCLK_DRV_PHASE_A

#[repr(u8)]
pub enum CCLK_DRV_PHASE_A {
    ENUM_0_DEG,
    ENUM_90_DEG,
    ENUM_180_DEG,
    ENUM_270_DEG,
}

Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.

Value on reset: 0

Variants

ENUM_0_DEG

0: 0 degree shift.

ENUM_90_DEG

1: 90 degree shift.

ENUM_180_DEG

2: 180 degree shift.

ENUM_270_DEG

3: 270 degree shift.

Trait Implementations

impl Clone for CCLK_DRV_PHASE_A

fn clone(&self) -> CCLK_DRV_PHASE_A

Returns a copy of the value.

pub fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for CCLK_DRV_PHASE_A

impl Debug for CCLK_DRV_PHASE_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq<CCLK_DRV_PHASE_A> for CCLK_DRV_PHASE_A

fn eq(&self, other: &CCLK_DRV_PHASE_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]

pub fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for CCLK_DRV_PHASE_A