[−][src]Module lpc55_pac::usart0
USARTs
Modules
addr | Address register for automatic address matching. |
brg | Baud Rate Generator register. 16-bit integer baud rate divisor value. |
cfg | USART Configuration register. Basic USART configuration settings that typically are not changed during operation. |
ctl | USART Control register. USART control settings that are more likely to change during operation. |
fifocfg | FIFO configuration and enable register. |
fifointenclr | FIFO interrupt enable clear (disable) and read register. |
fifointenset | FIFO interrupt enable set (enable) and read register. |
fifointstat | FIFO interrupt status register. |
fiford | FIFO read data. |
fifordnopop | FIFO data read with no FIFO pop. |
fifostat | FIFO status register. |
fifotrig | FIFO trigger settings for interrupt and DMA request. |
fifowr | FIFO write data. |
id | Peripheral identification register. |
intenclr | Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. |
intenset | Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
intstat | Interrupt status register. Reflects interrupts that are currently enabled. |
osr | Oversample selection register for asynchronous communication. |
stat | USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. |
Structs
RegisterBlock | Register block |
Type Definitions
ADDR | Address register for automatic address matching. |
BRG | Baud Rate Generator register. 16-bit integer baud rate divisor value. |
CFG | USART Configuration register. Basic USART configuration settings that typically are not changed during operation. |
CTL | USART Control register. USART control settings that are more likely to change during operation. |
FIFOCFG | FIFO configuration and enable register. |
FIFOINTENCLR | FIFO interrupt enable clear (disable) and read register. |
FIFOINTENSET | FIFO interrupt enable set (enable) and read register. |
FIFOINTSTAT | FIFO interrupt status register. |
FIFORD | FIFO read data. |
FIFORDNOPOP | FIFO data read with no FIFO pop. |
FIFOSTAT | FIFO status register. |
FIFOTRIG | FIFO trigger settings for interrupt and DMA request. |
FIFOWR | FIFO write data. |
ID | Peripheral identification register. |
INTENCLR | Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. |
INTENSET | Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. |
INTSTAT | Interrupt status register. Reflects interrupts that are currently enabled. |
OSR | Oversample selection register for asynchronous communication. |
STAT | USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. |