Struct lpc43xx::emc::staticconfig::W
[−]
[src]
pub struct W { /* fields omitted */ }Value to write to the register
Methods
impl W[src]
pub fn reset_value() -> W[src]
Reset value of the register
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self[src]
Writes raw bits to the register
pub fn mw(&mut self) -> _MWW[src]
Bits 0:1 - Memory width.
pub fn pm(&mut self) -> _PMW[src]
Bit 3 - Page mode. In page mode the EMC can burst up to four external accesses. Therefore devices with asynchronous page mode burst four or higher devices are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.
pub fn pc(&mut self) -> _PCW[src]
Bit 6 - Chip select polarity. The value of the chip select polarity on power-on reset is 0.
pub fn pb(&mut self) -> _PBW[src]
Bit 7 - Byte lane state. The byte lane state bit, PB, enables different types of memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable). In this case for reads all the BLSn[3:0] bits must be HIGH. This means that the byte lane state (PB) bit must be LOW. 16 bit wide static memory devices usually have the BLSn[3:0] signals connected to the UBn and LBn (upper byte and lower byte) signals in the static memory. In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW. For reads, all the UB and LB signals must be asserted LOW so that the bus is driven. In this case the byte lane state (PB) bit must be HIGH. When PB is set to 0, the WE signal is undefined or 0. You must set PB to 1, to use the WE signal.
pub fn ew(&mut self) -> _EWW[src]
Bit 8 - Extended wait. Extended wait (EW) uses the StaticExtendedWait register to time both the read and write transfers rather than the StaticWaitRd and StaticWaitWr registers. This enables much longer transactions.[1]
pub fn b(&mut self) -> _BW[src]
Bit 19 - Buffer enable [2].
pub fn p(&mut self) -> _PW[src]
Bit 20 - Write protect.