[−][src]Struct lpc176x_5x::syscon::usbclkcfg::R
Value read from the register
Methods
impl R[src]
pub fn bits(&self) -> u32[src]
Value of the register as raw bits
pub fn usbsel(&self) -> USBSELR[src]
Bits 0:3 - Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz.
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🔬 This is a nightly-only experimental API. (
try_from)The type returned in the event of a conversion error.
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