Struct RegisterBlock 

pub struct RegisterBlock {
    pub lcr: Reg<LCR_SPEC>,
    pub mcr: Reg<MCR_SPEC>,
    pub lsr: Reg<LSR_SPEC>,
    pub msr: Reg<MSR_SPEC>,
    pub scr: Reg<SCR_SPEC>,
    pub acr: Reg<ACR_SPEC>,
    pub fdr: Reg<FDR_SPEC>,
    pub ter: Reg<TER_SPEC>,
    pub rs485ctrl: Reg<RS485CTRL_SPEC>,
    pub rs485adrmatch: Reg<RS485ADRMATCH_SPEC>,
    pub rs485dly: Reg<RS485DLY_SPEC>,
    /* private fields */
}

Register block

Fields

lcr: Reg<LCR_SPEC>

0x0c - Line Control Register. Contains controls for frame formatting and break generation.

mcr: Reg<MCR_SPEC>

0x10 - Modem Control Register. Contains controls for flow control handshaking and loopback mode.

lsr: Reg<LSR_SPEC>

0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors.

msr: Reg<MSR_SPEC>

0x18 - Modem Status Register. Contains handshake signal status flags.

scr: Reg<SCR_SPEC>

0x1c - Scratch Pad Register. 8-bit temporary storage for software.

acr: Reg<ACR_SPEC>

0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature.

fdr: Reg<FDR_SPEC>

0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider.

ter: Reg<TER_SPEC>

0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control.

rs485ctrl: Reg<RS485CTRL_SPEC>

0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.

rs485adrmatch: Reg<RS485ADRMATCH_SPEC>

0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.

rs485dly: Reg<RS485DLY_SPEC>

0x54 - RS-485/EIA-485 direction control delay.

Implementations

impl RegisterBlock

pub fn dll(&self) -> &Reg<DLL_SPEC>

0x00 - DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

pub fn thr(&self) -> &Reg<THR_SPEC>

0x00 - DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.

pub fn rbr(&self) -> &Reg<RBR_SPEC>

0x00 - DLAB =0 Receiver Buffer Register. Contains the next received character to be read.

pub fn ier(&self) -> &Reg<IER_SPEC>

0x04 - DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.

pub fn dlm(&self) -> &Reg<DLM_SPEC>

0x04 - DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.

pub fn fcr(&self) -> &Reg<FCR_SPEC>

0x08 - FIFO Control Register. Controls UART1 FIFO usage and modes.

pub fn iir(&self) -> &Reg<IIR_SPEC>

0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending.