Struct lis2dh12::Lis2dh12

pub struct Lis2dh12<I2C> { /* private fields */ }

LIS2DH12 driver

Implementations

impl<I2C, E> Lis2dh12<I2C>

where I2C: WriteRead<Error = E> + Write<Error = E>, E: Debug,

pub fn new(i2c: I2C, addr: SlaveAddr) -> Result<Self, Error<E>>

Create a new LIS2DH12 driver from the given I2C peripheral

pub fn destroy(self) -> I2C

Destroy driver instance, return I2C bus instance

pub fn get_device_id(&mut self) -> Result<u8, Error<E>>

WHO_AM_I register

pub fn set_mode(&mut self, mode: Mode) -> Result<(), Error<E>>

Operating mode selection, CTRL_REG1: LPen bit, CTRL_REG4: HR bit

pub fn set_odr(&mut self, odr: Odr) -> Result<(), Error<E>>

Data rate selection, CTRL_REG1: ODR

pub fn enable_axis( &mut self, (x, y, z): (bool, bool, bool) ) -> Result<(), Error<E>>

X,Y,Z-axis enable, CTRL_REG1: Xen, Yen, Zen

pub fn enable_hp_filter( &mut self, click: bool, ia2: bool, ia1: bool ) -> Result<(), Error<E>>

Enable high-pass filter for CLICK/IA2/IA1

pub fn enable_i1_click(&mut self, enable: bool) -> Result<(), Error<E>>

CLICK interrupt on INT1 pin, CTRL_REG3: I1_CLICK

pub fn enable_i1_ia1(&mut self, enable: bool) -> Result<(), Error<E>>

IA1 interrupt on INT1 pin, CTRL_REG3: I1_IA1

pub fn enable_i1_ia2(&mut self, enable: bool) -> Result<(), Error<E>>

IA2 interrupt on INT1 pin, CTRL_REG3: I1_IA2

pub fn enable_i1_zyxda(&mut self, enable: bool) -> Result<(), Error<E>>

ZYXDA interrupt on INT1 pin, CTRL_REG3: I2_ZYXDA

pub fn enable_i1_wtm(&mut self, enable: bool) -> Result<(), Error<E>>

FIFO watermark on INT1 pin, CTRL_REG3: I2_ZYXDA

pub fn get_stored_samples(&mut self) -> Result<u8, Error<E>>

Get the amount of samples currently stored in the FIFO queue

pub fn enable_i1_overrun(&mut self, enable: bool) -> Result<(), Error<E>>

FIFO overrun on INT1 pin, CTRL_REG3: I1_OVERRUN

pub fn set_bdu(&mut self, bdu: bool) -> Result<(), Error<E>>

Block data update, CTRL_REG4: BDU

pub fn set_fs(&mut self, fs: FullScale) -> Result<(), Error<E>>

Full-scale selection, CTRL_REG4: FS

pub fn reboot(&mut self, reboot: bool) -> Result<(), Error<E>>

Reboot memory content, CTRL_REG5: BOOT

pub fn in_boot(&mut self) -> Result<bool, Error<E>>

In boot, CTRL_REG5: BOOT

pub fn enable_fifo(&mut self, enable: bool) -> Result<(), Error<E>>

FIFO enable, CTRL_REG5: FIFO_EN

pub fn enable_lir_int1(&mut self, latch: bool) -> Result<(), Error<E>>

Latch interrupt request on INT1_SRC (31h), with INT1_SRC (31h) register cleared by reading INT1_SRC (31h) itself, CTRL_REG5: LIR_INT1

pub fn enable_d4d_int1(&mut self, enable: bool) -> Result<(), Error<E>>

4D enable: 4D detection is enabled on INT1 pin when 6D bit on INT1_CFG (30h) is set to 1, CTRL_REG5: D4D_INT1

pub fn enable_lir_int2(&mut self, latch: bool) -> Result<(), Error<E>>

Latch interrupt request on INT2_SRC (35h) register, with INT2_SRC (35h) register cleared by reading INT2_SRC (35h) itself, CTRL_REG5: LIR_INT2

pub fn enable_d4d_int2(&mut self, enable: bool) -> Result<(), Error<E>>

4D enable: 4D detection is enabled on INT2 pin when 6D bit on INT2_CFG (34h) is set to 1, CTRL_REG5: D4D_INT2

pub fn enable_i2_click(&mut self, enable: bool) -> Result<(), Error<E>>

CLICK interrupt on INT2 pin, CTRL_REG6: I2_CLICK

pub fn enable_i2_ia1(&mut self, enable: bool) -> Result<(), Error<E>>

IA1 interrupt on INT2 pin, CTRL_REG6: I2_IA1

pub fn enable_i2_ia2(&mut self, enable: bool) -> Result<(), Error<E>>

IA2 interrupt on INT2 pin, CTRL_REG6: I2_IA2

pub fn enable_i2_boot(&mut self, enable: bool) -> Result<(), Error<E>>

Boot interrupt on INT2 pin, CTRL_REG6: I2_BOOT

pub fn enable_i2_act(&mut self, enable: bool) -> Result<(), Error<E>>

Activity interrupt on INT2 pin, CTRL_REG6: I2_ACT

pub fn set_int_polarity(&mut self, active_low: bool) -> Result<(), Error<E>>

INT1/INT2 pin polarity, CTRL_REG6: INT_POLARITY

pub fn get_status(&mut self) -> Result<DataStatus, Error<E>>

Data status, STATUS_REG: as DataStatus {zyxor: ZYXOR, xyzor: (XOR, YOR, ZOR), zyxda: ZYXDA, xyzda: (XDA, YDA, ZDA)}

pub fn set_fm(&mut self, fm: FifoMode) -> Result<(), Error<E>>

FIFO mode selection, FIFO_CTRL_REG: FM

pub fn set_fth(&mut self, fth: u8) -> Result<(), Error<E>>

FIFO threshold, FIFO_CTRL_REG: FTH

pub fn disable_click(&mut self) -> Result<(), Error<E>>

Disable click interrupt, CLICK_CFG clean all bits

pub fn enable_double_click( &mut self, (x, y, z): (bool, bool, bool) ) -> Result<(), Error<E>>

Enable interrupt double-click on X,Y,Z axis, CLICK_CFG: XD, YD, ZD

pub fn enable_single_click( &mut self, (x, y, z): (bool, bool, bool) ) -> Result<(), Error<E>>

Enable interrupt single-click on X,Y,Z axis, CLICK_CFG: XS, YS, ZS

pub fn get_click_src( &mut self ) -> Result<Option<((bool, bool), bool, (bool, bool, bool))>, Error<E>>

Click source, CLICK_SRC decoded as ((DClick, SClick), Sign, (X, Y, Z))

pub fn enable_lir_click(&mut self, latch: bool) -> Result<(), Error<E>>

If the LIR_Click bit is not set, the interrupt is kept high for the duration of the latency window. If the LIR_Click bit is set, the interrupt is kept high until the CLICK_SRC (39h) register is read. CLICK_THS: LIR_Click

pub fn set_click_ths(&mut self, ths: u8) -> Result<(), Error<E>>

Click threshold, CLICK_THS: Ths

pub fn set_click_thsf(&mut self, ths: f32) -> Result<(), Error<E>>

Click threshold as f32, CLICK_THS: Ths

pub fn set_time_limit(&mut self, tli: u8) -> Result<(), Error<E>>

Click time limit, TIME_LIMIT: TLI

pub fn set_time_latency(&mut self, tla: u8) -> Result<(), Error<E>>

Click time latency, TIME_LATENCY: TLA

pub fn set_time_window(&mut self, tw: u8) -> Result<(), Error<E>>

Click time window, TIME_WINDOW: TW

pub fn set_act_ths(&mut self, ths: u8) -> Result<(), Error<E>>

Sleep-to-wake, return-to-sleep activation threshold in low-power mode, ACT_THS: Acth

pub fn set_act_thsf(&mut self, ths: f32) -> Result<(), Error<E>>

Sleep-to-wake, return-to-sleep activation threshold as f32, ACT_THS: Acth

pub fn set_act_dur(&mut self, d: u8) -> Result<(), Error<E>>

Sleep-to-wake, return-to-sleep duration, ACT_DUR: ActD

pub fn enable_temp(&mut self, enable: bool) -> Result<(), Error<E>>

Temperature sensor enable, TEMP_CFG_REG: TEMP_EN, the BDU bit in CTRL_REG4 is also set

pub fn get_temp_status(&mut self) -> Result<(bool, bool), Error<E>>

Temperature data status, STATUS_REG_AUX: TOR - Temperature data overrun, TDA - Temperature new data available

pub fn get_temp_out(&mut self) -> Result<(i8, u8), Error<E>>

Temperature sensor data, OUT_TEMP_H, OUT_TEMP_L

pub fn get_temp_outf(&mut self) -> Result<f32, Error<E>>

Temperature sensor data as float, OUT_TEMP_H, OUT_TEMP_L converted to f32

pub fn set_ref(&mut self, reference: u8) -> Result<(), Error<E>>

REFERENCE register

pub fn get_ref(&mut self) -> Result<u8, Error<E>>

REFERENCE register

pub fn int1(&mut self) -> Int<'_, Int1Regs, I2C>

INT1

pub fn int2(&mut self) -> Int<'_, Int2Regs, I2C>

INT2

pub fn reset(&mut self) -> Result<(), Error<E>>

Resets all registers to their default

pub fn enable_st0(&mut self, enable: bool) -> Result<(), Error<E>>

Enable self test 0, this shouldn’t be enabled at the same time as self test 1

pub fn enable_st1(&mut self, enable: bool) -> Result<(), Error<E>>

Enable self test 1, this shouldn’t be enabled at the same time as self test 0

pub fn dump_regs<W>(&mut self, w: &mut W) -> Result<(), Error<E>>

where W: Write,

Dump registers

Trait Implementations

impl<I2C, E> Accelerometer for Lis2dh12<I2C>

where I2C: WriteRead<Error = E> + Write<Error = E>, E: Debug,

fn accel_norm(&mut self) -> Result<F32x3, Error<E>>

Get normalized ±g reading from the accelerometer

fn sample_rate(&mut self) -> Result<f32, Error<Self::Error>>

Get sample rate of accelerometer in Hz

type Error = E

Error type

impl<I2C, E> RawAccelerometer<I16x3> for Lis2dh12<I2C>

where I2C: WriteRead<Error = E> + Write<Error = E>, E: Debug,

fn accel_raw(&mut self) -> Result<I16x3, Error<E>>

Get acceleration reading from the accelerometer

type Error = E

Error type