pub trait Chip:
Debug
+ Send
+ Sync {
// Required methods
fn pin_count(&self) -> usize;
fn get_pin_type(&self, pin: usize) -> PinType;
fn set_input(&mut self, pin: usize, level: LogicLevel);
fn get_output(&self, pin: usize) -> LogicLevel;
fn update(&mut self);
fn name(&self) -> &'static str;
fn box_clone(&self) -> Box<dyn Chip>;
}
Expand description
Trait representing a TTL chip.
Chips are composed of internal gates and have external pins.
They maintain the state of their pins and update their outputs based on inputs.
The update
method simulates one clock cycle or propagation delay step.
Required Methods§
Sourcefn get_pin_type(&self, pin: usize) -> PinType
fn get_pin_type(&self, pin: usize) -> PinType
Sourcefn set_input(&mut self, pin: usize, level: LogicLevel)
fn set_input(&mut self, pin: usize, level: LogicLevel)
Sourcefn get_output(&self, pin: usize) -> LogicLevel
fn get_output(&self, pin: usize) -> LogicLevel
Sourcefn update(&mut self)
fn update(&mut self)
Updates the chip’s internal state. This typically involves:
- Reading the current state of input pins.
- Propagating these levels through the internal gates.
- Updating the state of the output pins based on the gate results. This method simulates a clock tick or propagation delay for combinational logic.