Enum ParseError

pub enum ParseError {
    UndefinedError(String),
    CyclicDependency,
    InvalidUTF8,
    InvalidVerilog(String),
    MissingModules(Vec<String>),
    PortsWithoutDirection(String, Vec<String>),
    UndeclaredNets(Vec<String>),
    AssignmentWidthMismatch(Vec<(LValue, Expr)>),
    PortConnectionMismatch,
    PortConnectionWidthMismatch,
}

Error type returned by the Verilog reader.

Variants

UndefinedError(String)

Some unspecified error.

CyclicDependency

Modules have a cyclic dependency. (Recursive module instantiation)

InvalidUTF8

The Verilog data is not UTF-8 encoded.

InvalidVerilog(String)

The syntax is not not accepted. Contains an error message string.

MissingModules(Vec<String>)

Some modules are not known yet. Contains names of the missing modules.

PortsWithoutDirection(String, Vec<String>)

Some module ports are neither declared as input nor output. Contains module name and list of affected module ports.

UndeclaredNets(Vec<String>)

Some nets are used but not declared with a wire/input/output/inout statement.

AssignmentWidthMismatch(Vec<(LValue, Expr)>)

Bit width is wrong in an assignment.

PortConnectionMismatch

Mismatch of number of ports in port connection of a module instantiation.

PortConnectionWidthMismatch

Bit-width mismatch in a port connection.

Trait Implementations

impl Clone for ParseError

fn clone(&self) -> ParseError

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ParseError

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for ParseError

fn eq(&self, other: &ParseError) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for ParseError

impl StructuralPartialEq for ParseError