Enum libreda_structural_verilog::ParseError [−][src]
pub enum ParseError {
UndefinedError(String),
CyclicDependency,
InvalidUTF8,
InvalidVerilog(String),
MissingModules(Vec<String>),
PortsWithoutDirection(String, Vec<String>),
UndeclaredNets(Vec<String>),
AssignmentWidthMismatch(Vec<(LValue, Expr)>),
PortConnectionMismatch,
PortConnectionWidthMismatch,
}
Expand description
Error type returned by the Verilog reader.
Variants
UndefinedError(String)
Tuple Fields
0: String
Some unspecified error.
CyclicDependency
Modules have a cyclic dependency. (Recursive module instantiation)
InvalidUTF8
The Verilog data is not UTF-8 encoded.
InvalidVerilog(String)
Tuple Fields
0: String
The syntax is not not accepted. Contains an error message string.
MissingModules(Vec<String>)
Some modules are not known yet. Contains names of the missing modules.
PortsWithoutDirection(String, Vec<String>)
Some module ports are neither declared as input nor output. Contains module name and list of affected module ports.
UndeclaredNets(Vec<String>)
Some nets are used but not declared with a wire
/input
/output
/inout
statement.
AssignmentWidthMismatch(Vec<(LValue, Expr)>)
Bit width is wrong in an assignment.
PortConnectionMismatch
Mismatch of number of ports in port connection of a module instantiation.
PortConnectionWidthMismatch
Bit-width mismatch in a port connection.
Trait Implementations
This method tests for self
and other
values to be equal, and is used
by ==
. Read more
This method tests for !=
.
Auto Trait Implementations
impl RefUnwindSafe for ParseError
impl Send for ParseError
impl Sync for ParseError
impl Unpin for ParseError
impl UnwindSafe for ParseError
Blanket Implementations
Mutably borrows from an owned value. Read more
Compare self to key
and return true
if they are equal.