Struct ClockAwareInterconnectModel 

pub struct ClockAwareInterconnectModel<M> { /* private fields */ }

Wrapper around interconnect delay models.

Used to keep the link between signals and their clock domains. The data-structure is zero-cost for the interconnect model. The data-structure for the signals gets larger because of the additional clock ID.

Implementations

impl<M> ClockAwareInterconnectModel<M>

pub fn new(inner_model: M) -> Self

Wrap an interconnect model. This is zero-cost. Best use a reference type as the inner model.

Trait Implementations

impl<M: Clone> Clone for ClockAwareInterconnectModel<M>

fn clone(&self) -> ClockAwareInterconnectModel<M>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<M: Debug> Debug for ClockAwareInterconnectModel<M>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<M> DelayBase for ClockAwareInterconnectModel<M>

where M: DelayBase,

Delegate trait implementation to the inner model.

type Delay = <M as DelayBase>::Delay

Type representing a delay. This can be as simple as a f64 or more complicated such as a probability distribution.

fn summarize_delays( &self, signal1: &Self::Signal, signal2: &Self::Signal, ) -> Self::Signal

Summarize multiple possible output signals into one signal. Depending on the timing analysis mode (late/early) this might be a max or min function.

fn get_delay(&self, from: &Self::Signal, to: &Self::Signal) -> Self::Delay

Compute the delay from one signal to another signal.

impl<M, N> InterconnectDelayModel<N> for ClockAwareInterconnectModel<M>

where N: NetlistBase, M: InterconnectDelayModel<N>,

fn interconnect_output( &self, netlist: &N, source_terminal: &TerminalId<N>, input_signal: &Self::Signal, target_terminal: &TerminalId<N>, output_load: &Self::Load, ) -> Option<Self::Signal>

Compute the cell delay from the source_terminal to the target_terminal.

impl<M> LoadBase for ClockAwareInterconnectModel<M>

where M: LoadBase,

Delegate trait implementation to the inner model.

type Load = <M as LoadBase>::Load

An electrical load. Typically a capacitance.

fn sum_loads(&self, load1: &Self::Load, load2: &Self::Load) -> Self::Load

Compute the sum of two loads.

impl<M> TimingBase for ClockAwareInterconnectModel<M>

where M: TimingBase,

Delegate trait implementation to the inner model.

type Signal = SignalWithClock<<M as TimingBase>::Signal>

Representation of signals at input or output pins. In case of the Non-linear delay model (NLDM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

type LogicValue = <M as TimingBase>::LogicValue

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.