Struct LibertyTimingLibrary 

pub struct LibertyTimingLibrary<CellId, PinId> { /* private fields */ }

Timing library based on a ‘liberty’ library.

Implementations

impl<CellId, PinId> LibertyTimingLibrary<CellId, PinId>

where CellId: Hash + Eq + Clone, PinId: Hash + Eq + Clone,

pub fn new( lib: &Group, cell_by_name: impl Fn(&str) -> Option<CellId>, pin_by_name: impl Fn(&CellId, &str) -> Option<PinId>, ) -> Result<Self, LibertyErr>

Create a new timing library based on a liberty structure.

impl<CellId, PinId> LibertyTimingLibrary<CellId, PinId>

where CellId: Hash + Eq, PinId: Hash + Eq + Clone,

pub fn get_pin(&self, cell: &CellId, output_pin: &PinId) -> Option<&Pin<PinId>>

Find a pin by the name of the cell and the name of the pin.

Trait Implementations

impl<CellId: Clone, PinId: Clone> Clone for LibertyTimingLibrary<CellId, PinId>

fn clone(&self) -> LibertyTimingLibrary<CellId, PinId>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<CellId: Debug, PinId: Debug> Debug for LibertyTimingLibrary<CellId, PinId>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<CellId, PinId> TimingLibrary for LibertyTimingLibrary<CellId, PinId>

where CellId: Hash + Eq, PinId: Hash + Eq + Clone,

type CellId = CellId

ID type for cells.

type PinId = PinId

ID type for pins.

fn get_slew( &self, arc: DelayArcArg<'_, CellId, PinId>, input_slew: Time, output_capacitance: Capacitance, ) -> Option<Time>

Get the transition time (slew) of an output pin. The transition time is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

fn get_cell_delay( &self, arc: DelayArcArg<'_, CellId, PinId>, input_slew: Time, output_capacitance: Capacitance, ) -> Option<Time>

Get the signal propagation time from the related_pin to the output_pin. The delay is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

fn get_hold_constraint( &self, arc: ConstraintArcArg<'_, CellId, PinId>, related_pin_transition: Time, constrained_pin_transition: Time, output_load: Capacitance, ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).

fn get_setup_constraint( &self, arc: ConstraintArcArg<'_, CellId, PinId>, related_pin_transition: Time, constrained_pin_transition: Time, output_load: Capacitance, ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).