Trait libreda_sta::traits::timing_base::TimingBase

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pub trait TimingBase: LoadBase {
    type Signal: Signal<LogicValue = Self::LogicValue>;
    type LogicValue: Copy + Clone + Debug + Default + Sync + Send + From<bool> + TryInto<bool>;
}
Expand description

Defines the concept of signals (e.g. slew rates and actual arrival times) and output loads (e.g. load capacitance).

Required Associated Types§

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type Signal: Signal<LogicValue = Self::LogicValue>

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

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type LogicValue: Copy + Clone + Debug + Default + Sync + Send + From<bool> + TryInto<bool>

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.

Implementations on Foreign Types§

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impl<TB: TimingBase + ?Sized> TimingBase for &TB

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type Signal = <TB as TimingBase>::Signal

Representation of signals at input or output pins. In case of the Non-linear delay model (NDLM) this could be a bundle of the slew rate and the delay but also the polarity of the signal. But this type could as well also be a statistical representation of a signal, e.g. a probability distribution of arrival times.

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type LogicValue = <TB as TimingBase>::LogicValue

Type of logic value. Typically this might be a three-valued type which represents logical 0, 1 and ‘unknown’. The default is typically ‘unknown’. This is used to specify static input signals when evaluating cell delays or constraints.

Implementors§