Trait libreda_sta::TimingLibrary

pub trait TimingLibrary {
    type CellId;
    type PinId;

    // Required methods
    fn get_slew(
        &self,
        arc: DelayArcArg<'_, Self::CellId, Self::PinId>,
        input_slew: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
    fn get_cell_delay(
        &self,
        arc: DelayArcArg<'_, Self::CellId, Self::PinId>,
        input_slew: Time,
        output_capacitance: Capacitance
    ) -> Option<Time>;
    fn get_hold_constraint(
        &self,
        arc: ConstraintArcArg<'_, Self::CellId, Self::PinId>,
        related_pin_transition: Time,
        constrained_pin_transition: Time,
        output_load: Capacitance
    ) -> Option<Time>;
    fn get_setup_constraint(
        &self,
        arc: ConstraintArcArg<'_, Self::CellId, Self::PinId>,
        related_pin_transition: Time,
        constrained_pin_transition: Time,
        output_load: Capacitance
    ) -> Option<Time>;
}

Public exports. Query cell delays and setup/hold constraints.

Required Associated Types

type CellId

ID type for cells.

type PinId

ID type for pins.

Required Methods

fn get_slew( &self, arc: DelayArcArg<'_, Self::CellId, Self::PinId>, input_slew: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the transition time (slew) of an output pin. The transition time is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

fn get_cell_delay( &self, arc: DelayArcArg<'_, Self::CellId, Self::PinId>, input_slew: Time, output_capacitance: Capacitance ) -> Option<Time>

Get the signal propagation time from the related_pin to the output_pin. The delay is dependent on the input transition time input_slew and the capacitive load at the output pin output_capacitance.

fn get_hold_constraint( &self, arc: ConstraintArcArg<'_, Self::CellId, Self::PinId>, related_pin_transition: Time, constrained_pin_transition: Time, output_load: Capacitance ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).

• constrained_edge_polarity: Polarity of the constrained edge.
• edge_polarity: Polarity of the related edge.

fn get_setup_constraint( &self, arc: ConstraintArcArg<'_, Self::CellId, Self::PinId>, related_pin_transition: Time, constrained_pin_transition: Time, output_load: Capacitance ) -> Option<Time>

Get the a constraint between edges of two input signals. The ‘constrained’ edge is usually some data signal with is constrained by a clock signal (also called ‘related’ edge).

• constrained_edge_polarity: Polarity of the constrained edge.
• edge_polarity: Polarity of the related edge.

Implementors

impl<CellId, PinId> TimingLibrary for LibertyTimingLibrary<CellId, PinId>

where CellId: Hash + Eq, PinId: Hash + Eq + Clone,

type CellId = CellId

type PinId = PinId