pub trait SimpleBufferInsertion<LN: LayoutEdit + NetlistEdit>{
type Error;
// Required method
fn insert_buffers(
&self,
chip: &mut LN,
signal_source: TerminalId<LN>,
signal_sinks: &Vec<TerminalId<LN>>,
) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error>;
// Provided method
fn add_buffer_tree_on_net(
&self,
chip: &mut LN,
net: &LN::NetId,
) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error> { ... }
}Expand description
Create a simple buffer tree between a specified source pin and a set of sink pins. The insertion strategy is up to the trait implementation.
Required Associated Types§
Required Methods§
Sourcefn insert_buffers(
&self,
chip: &mut LN,
signal_source: TerminalId<LN>,
signal_sinks: &Vec<TerminalId<LN>>,
) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error>
fn insert_buffers( &self, chip: &mut LN, signal_source: TerminalId<LN>, signal_sinks: &Vec<TerminalId<LN>>, ) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error>
Create a buffer tree between the source terminal and the sinks. The terminals are given together with their location to enable creation of a placement-aware buffer tree.
On success: Return a list of created cell instances and a list of created nets.
§Note
All further information (which buffer to use, how many buffers to place, where to place them, etc.) is to be defined by the implementation of this trait.
Provided Methods§
Sourcefn add_buffer_tree_on_net(
&self,
chip: &mut LN,
net: &LN::NetId,
) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error>
fn add_buffer_tree_on_net( &self, chip: &mut LN, net: &LN::NetId, ) -> Result<(Vec<LN::CellInstId>, Vec<LN::NetId>), Self::Error>
Replace the net by a buffer tree.
- Identify signal driver and sinks by the direction of the pins.
- Call
insert_buffers().
On success: Return a list of created cell instances and a list of created nets.