Struct Model 

pub struct Model<C: Ctx> {

    pub name: String,
    pub cell_name: Option<String>,
    pub short: Vec<Vec<String>>,
    pub extra_ctx: C::Cell,
    pub attributes: Attributes,
    pub area: Option<f64>,
    pub dont_use: Option<bool>,
    pub dont_touch: Option<bool>,
    pub single_bit_degenerate: Option<String>,
    pub driver_waveform_rise: Option<String>,
    pub driver_waveform_fall: Option<String>,
    pub always_on: Option<bool>,
    pub antenna_diode_type: Option<AntennaDiodeType>,
    pub clock_gating_integrated_cell: Option<ClockGatingIntegratedCell>,
    pub cell_footprint: Option<String>,
    pub cell_leakage_power: Option<f64>,
    pub em_temp_degradation_factor: Option<f64>,
    pub fpga_cell_type: Option<FpgaCellType>,
    pub fpga_isd: Option<String>,
    pub interface_timing: Option<bool>,
    pub io_type: Option<String>,
    pub is_filler_cell: Option<bool>,
    pub is_pad: Option<bool>,
    pub is_pll_cell: Option<bool>,
    pub is_clock_gating_cell: Option<bool>,
    pub is_clock_isolation_cell: Option<bool>,
    pub is_isolation_cell: Option<bool>,
    pub is_level_shifter: Option<bool>,
    pub is_macro_cell: Option<bool>,
    pub is_soi: Option<bool>,
    pub level_shifter_type: Option<LevelShifterType>,
    pub retention_cell: Option<String>,
    pub switch_cell_type: Option<SwitchCellType>,
    pub sensitization_master: Option<String>,
    pub dc_current: Option<TableLookUp2D<C>>,
    pub input_voltage_range: Option<(f64, f64)>,
    pub output_voltage_range: Option<(f64, f64)>,
    pub pin_opposite: Option<PinOpposite>,
    pub char_config: Option<CharConfig<C>>,
    pub pg_pin: GroupSet<PgPin<C>>,
    pub ff: GroupSet<FF<C>>,
    pub ff_bank: GroupSet<FFBank<C>>,
    pub latch: GroupSet<Latch<C>>,
    pub latch_bank: GroupSet<LatchBank<C>>,
    pub leakage_power: GroupSet<LeakagePower<C>>,
    pub statetable: Option<Statetable<C>>,
    pub dynamic_current: GroupSet<DynamicCurrent<C>>,
    pub intrinsic_parasitic: GroupSet<IntrinsicParasitic<C>>,
    pub preset_condition: Vec<RresetCondition<C>>,
    pub retention_condition: Vec<RetentionCondition<C>>,
    pub leakage_current: GroupSet<LeakageCurrent<C>>,
    pub pin: GroupSet<Pin<C>>,
    pub bus: GroupSet<Bus<C>>,
    pub test_cell: Vec<TestCell<C>>,
    pub bundle: GroupSet<Bundle<C>>,
    /* private fields */
}

A model group can include all the attributes that are valid in a cell group, as well as the two additional attributes described in this section. For information about the cell group attributes, see Attributes and Values on page 99. Reference

Fields

name: String

cell_name: Option<String>

The cell_name attribute specifies the name of the cell within a model group Reference-Definition

short: Vec<Vec<String>>

The short attribute lists the shorted ports that are connected together by a metal or poly trace. These ports are modeled within a model group. The most common example of a shorted port is a feedthrough, where an input port is directly connected to an output port and there is no active logic between these two ports.

Example 30 Using the short Attribute in a model Group

model(cellA) {
  area : 0.4;
  ...
  short(b, y);
  short(c, y);
  short(b, c);
  ...
  pin(y) {
    direction : output;
    timing() {
      related_pin : a;
      ...
    }
  }
  pin(a) {
    direction : input;
    capacitance : 0.1;
  }
  pin(b) {
    direction : input;
    capacitance : 0.1;
  }
  pin(c) {
    direction : input;
    capacitance : 0.1;
    clock : true;
  }
}

Reference-Definition

extra_ctx: C::Cell

attributes: Attributes

group undefined attributes

area: Option<f64>

dont_use: Option<bool>

The dont_use attribute with a true value indicates that a cell should not be added to a design during optimization Reference

dont_touch: Option<bool>

The dont_touch attribute with a true value indicates that all instances of the cell must remain in the network. Reference

single_bit_degenerate: Option<String>

CellId

driver_waveform_rise: Option<String>

driver_waveform_fall: Option<String>

always_on: Option<bool>

The always_on simple attribute models always-on cells or signal pins. Specify the attribute at the cell level to determine whether a cell is an always-on cell. Specify the attribute at the pin level to determine whether a pin is an always-on signal pin. Reference-Instance

antenna_diode_type: Option<AntennaDiodeType>

Reference-Instance

clock_gating_integrated_cell: Option<ClockGatingIntegratedCell>

You can use the clock_gating_integrated_cell attribute to enter specific values that determine which integrated cell functionality the clock-gating tool uses.

Syntax:

clock_gating_integrated_cell:generic|value_id;

Reference

cell_footprint: Option<String>

cell_leakage_power: Option<f64>

Use the cell_leakage_power attribute to define the leakage power of a cell. You must define this attribute for cells with state-dependent leakage power. If cell_leakage_power is missing or negative, the value of the default_cell_leakage_power attribute defined in the library is assumed. Reference

em_temp_degradation_factor: Option<f64>

The em_temp_degradation_factor attribute specifies the electromigration exponential degradation factor Reference

fpga_cell_type: Option<FpgaCellType>

interprets a combination timing arc between the clock pin and the output pin as a rising edge arc or as a falling edge arc

Valid values are rising_edge_clock_cell and falling_edge_clock_cell. Reference

fpga_isd: Option<String>

Use the fpga_isd attribute to reference the drive, io_type, and slew information contained in a library-level fpga_isd group. Reference

interface_timing: Option<bool>

Indicates that the timing arcs are interpreted according to interface timing specifications semantics. If this attribute is missing or its value is set to false, the timing relationships are interpreted as those of a regular cell rather than according to interface timing specification semantics. Reference

io_type: Option<String>

Use the io_type attribute to define the I/O standard used by this I/O cell. Reference

is_filler_cell: Option<bool>

is_pad: Option<bool>

The is_pad attribute identifies a pad pin on any I/O cell. You can also specify the is_pad attribute on PG pins. The valid values are true and false. If the cell-level pad_cell attribute is specified on a I/O cell, the is_pad attribute must be set to true in either a pg_pin group or on a signal pin for that cell. Reference

is_pll_cell: Option<bool>

The is_pll_cell Boolean attribute identifies a phase-locked loop cell. A phase-locked loop (PLL) is a feedback control system that automatically adjusts the phase of a locally-generated signal to match the phase of an input signal. Reference

is_clock_gating_cell: Option<bool>

The cell-level is_clock_gating_cell attribute specifies that a cell is for clock gating. Reference

is_clock_isolation_cell: Option<bool>

The is_clock_isolation_cell attribute identifies a cell as a clock-isolation cell. The default is false, meaning that the cell is a standard cell. For information about pin-level attributes of the clock-isolation cell, Reference

is_isolation_cell: Option<bool>

The cell-level is_isolation_cell attribute specifies that a cell is an isolation cell. The pin-level isolation_cell_enable_pin attribute specifies the enable input pin for the isolation cell. Reference

is_level_shifter: Option<bool>

The cell-level is_level_shifter attribute specifies that a cell is a level shifter cell. The pin-level level_shifter_enable_pin
attribute specifies the enable input pin for the level shifter cell. Reference

is_macro_cell: Option<bool>

The is_macro_cell simple Boolean attribute identifies whether a cell is a macro cell. If the attribute is set to true, the cell is a macro cell. If it is set to false, the cell is not a macro cell. Reference

is_soi: Option<bool>

The is_soi attribute specifies that the cell is a silicon-on-insulator (SOI) cell. The default is false, which means that the cell is a bulk-CMOS cell.

If the is_soi attribute is specified at both the library and cell levels, the cell-level value overrides the library-level value Reference

level_shifter_type: Option<LevelShifterType>

The level_shifter_type attribute specifies the voltage conversion type that is supported. Valid values are:

• LH: Low to High
• HL: High to Low
• HL_LH: High to Low and Low to HighThe

level_shifter_type attribute is optional Reference

retention_cell: Option<String>

The retention_cell attribute identifies a retention cell. The retention_cell_style value is a random string

Syntax

retention_cell : retention_cell_style ;

Reference

switch_cell_type: Option<SwitchCellType>

The switch_cell_type cell-level attribute specifies the type of the switch cell for direct inference.

Syntax:

switch_cell_type : coarse_grain | fine_grain;

Reference-Definition

sensitization_master: Option<String>

The sensitization_master attribute defines the sensitization group referenced by the cell to generate stimuli for characterization. The attribute is required if the cell contains sensitization information. Its string value should be any sensitization group name predefined in the current library.

Syntax

sensitization_master : sensitization_group_name;

sensitization_group_name

A string identifying the sensitization group name predefined in the current library.

Example

sensitization_master : sensi_2in_1out;

Reference

dc_current: Option<TableLookUp2D<C>>

Use the dc_current group to specify the input and output voltage values of a two-dimensional current table for a channel-connecting block.

Use index_1 to represent the input voltage and index_2 to represent the output voltage. The values attribute of the group lists the relative channel-connecting block DC current values in library units measured at the channel-connecting block output node. Reference-Definition

input_voltage_range: Option<(f64, f64)>

The input_voltage_range attribute specifies the allowed voltage range of the level-shifter input pin and the voltage range for all input pins of the cell under all possible operating conditions (defined across multiple libraries).

The attribute defines two floating values: the first is the lower bound, and second is the upper bound.

The input_voltage_range syntax differs from the pin-level input_signal_level_low and input_signal_level_high syntax in the following ways:

• The input_signal_level_low and input_signal_level_high attributes are defined on the input pins under one operating condition.
• The input_signal_level_low and input_signal_level_high attributes are used to specify the partial voltage swing of an input pin (that is, to prevent from swinging from ground rail VSS to full power rail VDD). Note that input_voltage_range is not related to the voltage swing.

Note:

The input_voltage_range and output_voltage_range attributes should always be defined together. Reference

output_voltage_range: Option<(f64, f64)>

The input_voltage_range and output_voltage_range attributes should always be defined together. Reference

pin_opposite: Option<PinOpposite>

Use the pin_opposite attribute to describe functionally opposite (logically inverse) groups of input or output pins.

Syntax

pin_opposite ("name_list1", "name_list2") ;

• name_list1: A name_list of output pins requires the supplied output values to be opposite.
• name_list2: A name_list of input pins requires the supplied input values to be opposite.

In the following example, pins IP and OP are logically inverse.

pin_opposite ("IP", "OP") ;

The pin_opposite attribute also incorporates the functionality of the pin_equal complex attribute.

In the following example, Q1, Q2, and Q3 are equal; QB1 and QB2 are equal; and the pins in the first group are opposite of the pins in the second group.

pin_opposite ("Q1 Q2 Q3", "QB1 QB2") ;

Reference

char_config: Option<CharConfig<C>>

The char_config group is a group of attributes including simple and complex attributes. These attributes represent library characterization configuration, and specify the settings to characterize the library. Use the char_config group syntax to apply an attribute value to a specific characterization model. You can specify multiple complex attributes in the char_config group. You can also specify a single complex attribute multiple times for different characterization models. You can also define the char_config group within the cell, pin, and timing groups. However, when you specify the same attribute in multiple char_config groups at different levels, such as at the library, cell, pin, and timing levels, the attribute specified at the lower level gets priority over the ones specified at the higher levels. For example, the pin-level char_config group attributes have higher priority over the library-level char_config group attributes.

Syntax

library (library_name) {
  char_config() {
    /* characterization configuration attributes */
  }
  ...
  cell (cell_name) {
    char_config() {
      /* characterization configuration attributes */
    }
    ...
    pin(pin_name) {
      char_config() {
        /* characterization configuration attributes */
      }
      timing() {
        char_config() {
          /* characterization configuration attributes */
        }
      } /* end of timing */
      ...
    } /* end of pin */
    ...
  } /* end of cell */
  ...
}

Reference

pg_pin: GroupSet<PgPin<C>>

ff: GroupSet<FF<C>>

ff_bank: GroupSet<FFBank<C>>

latch: GroupSet<Latch<C>>

latch_bank: GroupSet<LatchBank<C>>

leakage_power: GroupSet<LeakagePower<C>>

statetable: Option<Statetable<C>>

dynamic_current: GroupSet<DynamicCurrent<C>>

Use the dynamic_current group to specify a current waveform vector when the power and ground current is dependent on the logical condition of a cell. A dynamic_current group is defined in a cell group, as shown here: Reference

intrinsic_parasitic: GroupSet<IntrinsicParasitic<C>>

The intrinsic_parasitic group specifies the state-dependent intrinsic capacitance and intrinsic resistance of a cell.

Syntax

library( library_name ) {
  ......
  lu_table_template ( template_name ) {
    variable_1 : pg_voltage | pg_voltage_difference;
    index_1 ( "float, ..., float" );
  }
  cell (cell_name) {
    mode_definition (mode_name) {
      mode_value (mode_value) {
        when : boolean_expression ;
        sdf_cond : boolean_expression ;
      }
    }
    ...
    intrinsic_parasitic () {
      mode (mode_name, mode_value) ;
      when : boolean expression ;
      intrinsic_resistance(pg_pin_name) {
        related_output : output_pin_name ;
        value : float ;
        reference_pg_pin : pg_pin_name;
        lut_values ( template_name ) {
          index_1 ("float, ... float" );
          values ("float, ... float" );
        }
      }
      intrinsic_capacitance(pg_pin_name) {
        value : float ;
        reference_pg_pin : pg_pin_name;
        lut_values ( template_name ) {
          index_1 ("float, ... float" );
          values ("float, ... float" );
        }
      }
    }
  }
}

Simple Attributes

• when
• reference_pg_pin

Complex Attribute

• mode

Groups

• intrinsic_capacitance
• intrinsic_resistance
• total_capacitance Reference

preset_condition: Vec<RresetCondition<C>>

The preset_condition group is a group of attributes for a condition check on the normal mode preset expression.

If preset is asserted during the restore operation, it needs to extend beyond the restore operation time period so that the flip-flop content can be successfully overwritten. Therefore, trailing-edge condition checks on preset pins might be needed. Reference

retention_condition: Vec<RetentionCondition<C>>

The retention_condition group includes attributes that specify the conditions for the retention cell to hold its state during the retention mode. Reference

leakage_current: GroupSet<LeakageCurrent<C>>

A leakage_current group is defined within a cell group or a model group to specify leakage current values that are dependent on the state of the cell.

Syntax

library (name) {
cell(cell_name) {
  ...
  leakage_current() {
    when : boolean expression;
    pg_current(pg_pin_name) {
      value : float;
    }
    ...
  }
}

Simple Attributes

• when
• value

Complex Attribute

• mode

Group

• pg_current Reference

pin: GroupSet<Pin<C>>

bus: GroupSet<Bus<C>>

test_cell: Vec<TestCell<C>>

The test_cell group is in a cell group or model group. It models only the nontest behavior of a scan cell, which is described by an ff, ff_bank, latch, latch_bank or statetable statement and pin function attributes Reference

bundle: GroupSet<Bundle<C>>

Implementations

impl<C: Ctx> Model<C>

pub fn comments_this(&self) -> Option<&String>

pub fn comments_this_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_cell_name(&self) -> Option<&String>

pub fn comments_cell_name_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_area(&self) -> Option<&String>

pub fn comments_area_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_dont_use(&self) -> Option<&String>

pub fn comments_dont_use_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_dont_touch(&self) -> Option<&String>

pub fn comments_dont_touch_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_single_bit_degenerate(&self) -> Option<&String>

pub fn comments_single_bit_degenerate_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_driver_waveform_rise(&self) -> Option<&String>

pub fn comments_driver_waveform_rise_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_driver_waveform_fall(&self) -> Option<&String>

pub fn comments_driver_waveform_fall_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_always_on(&self) -> Option<&String>

pub fn comments_always_on_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_antenna_diode_type(&self) -> Option<&String>

pub fn comments_antenna_diode_type_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_clock_gating_integrated_cell(&self) -> Option<&String>

pub fn comments_clock_gating_integrated_cell_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_cell_footprint(&self) -> Option<&String>

pub fn comments_cell_footprint_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_cell_leakage_power(&self) -> Option<&String>

pub fn comments_cell_leakage_power_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_em_temp_degradation_factor(&self) -> Option<&String>

pub fn comments_em_temp_degradation_factor_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_fpga_cell_type(&self) -> Option<&String>

pub fn comments_fpga_cell_type_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_fpga_isd(&self) -> Option<&String>

pub fn comments_fpga_isd_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_interface_timing(&self) -> Option<&String>

pub fn comments_interface_timing_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_io_type(&self) -> Option<&String>

pub fn comments_io_type_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_is_filler_cell(&self) -> Option<&String>

pub fn comments_is_filler_cell_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_is_pad(&self) -> Option<&String>

pub fn comments_is_pad_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_is_pll_cell(&self) -> Option<&String>

pub fn comments_is_pll_cell_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_is_clock_gating_cell(&self) -> Option<&String>

pub fn comments_is_clock_gating_cell_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_is_clock_isolation_cell(&self) -> Option<&String>

pub fn comments_is_clock_isolation_cell_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_is_isolation_cell(&self) -> Option<&String>

pub fn comments_is_isolation_cell_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_is_level_shifter(&self) -> Option<&String>

pub fn comments_is_level_shifter_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_is_macro_cell(&self) -> Option<&String>

pub fn comments_is_macro_cell_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_is_soi(&self) -> Option<&String>

pub fn comments_is_soi_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_level_shifter_type(&self) -> Option<&String>

pub fn comments_level_shifter_type_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_retention_cell(&self) -> Option<&String>

pub fn comments_retention_cell_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

pub fn comments_switch_cell_type(&self) -> Option<&String>

pub fn comments_switch_cell_type_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_sensitization_master(&self) -> Option<&String>

pub fn comments_sensitization_master_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_input_voltage_range(&self) -> Option<&String>

pub fn comments_input_voltage_range_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_output_voltage_range(&self) -> Option<&String>

pub fn comments_output_voltage_range_entry<'a>( &'a mut self, ) -> Entry<'a, u64, String>

pub fn comments_pin_opposite(&self) -> Option<&String>

pub fn comments_pin_opposite_entry<'a>(&'a mut self) -> Entry<'a, u64, String>

Trait Implementations

impl<C: Ctx> Borrow<String> for Model<C>

fn borrow(&self) -> &ModelId

Immutably borrows from an owned value.

impl<C: Ctx> Borrow<str> for Model<C>

fn borrow(&self) -> &str

Immutably borrows from an owned value.

impl<C: Clone + Ctx> Clone for Model<C>

where C::Cell: Clone,

fn clone(&self) -> Model<C>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<C: Debug + Ctx> Debug for Model<C>

where C::Cell: Debug,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'de, C: Ctx> Deserialize<'de> for Model<C>

where C::Cell: Serialize + DeserializeOwned,

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl<C: Ctx> Item for Model<C>

type Id = String

type IdReadonlyItem = IdReadonlyModel<C>

unsafe fn __unsafe_deref_mut(&self) -> &mut Self::IdReadonlyItem

Safety

fn id(&self) -> &Self::Id

fn id_readonly(&mut self) -> &mut Self::IdReadonlyItem

impl<C: Ctx> Serialize for Model<C>

where C::Cell: Serialize + DeserializeOwned,

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.