Struct libamdgpu_top::AMDGPU::drm_amdgpu_info_device

#[repr(C)]
pub struct drm_amdgpu_info_device {

    pub device_id: u32,
    pub chip_rev: u32,
    pub external_rev: u32,
    pub pci_rev: u32,
    pub family: u32,
    pub num_shader_engines: u32,
    pub num_shader_arrays_per_engine: u32,
    pub gpu_counter_freq: u32,
    pub max_engine_clock: u64,
    pub max_memory_clock: u64,
    pub cu_active_number: u32,
    pub cu_ao_mask: u32,
    pub cu_bitmap: [[u32; 4]; 4],
    pub enabled_rb_pipes_mask: u32,
    pub num_rb_pipes: u32,
    pub num_hw_gfx_contexts: u32,
    pub pcie_gen: u32,
    pub ids_flags: u64,
    pub virtual_address_offset: u64,
    pub virtual_address_max: u64,
    pub virtual_address_alignment: u32,
    pub pte_fragment_size: u32,
    pub gart_page_size: u32,
    pub ce_ram_size: u32,
    pub vram_type: u32,
    pub vram_bit_width: u32,
    pub vce_harvest_config: u32,
    pub gc_double_offchip_lds_buf: u32,
    pub prim_buf_gpu_addr: u64,
    pub pos_buf_gpu_addr: u64,
    pub cntl_sb_buf_gpu_addr: u64,
    pub param_buf_gpu_addr: u64,
    pub prim_buf_size: u32,
    pub pos_buf_size: u32,
    pub cntl_sb_buf_size: u32,
    pub param_buf_size: u32,
    pub wave_front_size: u32,
    pub num_shader_visible_vgprs: u32,
    pub num_cu_per_sh: u32,
    pub num_tcc_blocks: u32,
    pub gs_vgt_table_depth: u32,
    pub gs_prim_buffer_depth: u32,
    pub max_gs_waves_per_vgt: u32,
    pub pcie_num_lanes: u32,
    pub cu_ao_bitmap: [[u32; 4]; 4],
    pub high_va_offset: u64,
    pub high_va_max: u64,
    pub pa_sc_tile_steering_override: u32,
    pub tcc_disabled_mask: u64,
    pub min_engine_clock: u64,
    pub min_memory_clock: u64,
    pub tcp_cache_size: u32,
    pub num_sqc_per_wgp: u32,
    pub sqc_data_cache_size: u32,
    pub sqc_inst_cache_size: u32,
    pub gl1c_cache_size: u32,
    pub gl2c_cache_size: u32,
    pub mall_size: u64,
    pub enabled_rb_pipes_mask_hi: u32,
    pub shadow_size: u32,
    pub shadow_alignment: u32,
    pub csa_size: u32,
    pub csa_alignment: u32,
}

Fields

device_id: u32

PCI Device ID

chip_rev: u32

Internal chip revision: A0, A1, etc.)

external_rev: u32

pci_rev: u32

Revision id in PCI Config space

family: u32

num_shader_engines: u32

num_shader_arrays_per_engine: u32

gpu_counter_freq: u32

max_engine_clock: u64

max_memory_clock: u64

cu_active_number: u32

cu_ao_mask: u32

cu_bitmap: [[u32; 4]; 4]

enabled_rb_pipes_mask: u32

Render backend pipe mask. One render backend is CB+DB.

num_rb_pipes: u32

num_hw_gfx_contexts: u32

pcie_gen: u32

ids_flags: u64

virtual_address_offset: u64

Starting virtual address for UMDs.

virtual_address_max: u64

The maximum virtual address

virtual_address_alignment: u32

Required alignment of virtual addresses.

pte_fragment_size: u32

Page table entry - fragment size

gart_page_size: u32

ce_ram_size: u32

constant engine ram size

vram_type: u32

video memory type info

vram_bit_width: u32

video memory bit width

vce_harvest_config: u32

gc_double_offchip_lds_buf: u32

prim_buf_gpu_addr: u64

pos_buf_gpu_addr: u64

cntl_sb_buf_gpu_addr: u64

param_buf_gpu_addr: u64

prim_buf_size: u32

pos_buf_size: u32

cntl_sb_buf_size: u32

param_buf_size: u32

wave_front_size: u32

num_shader_visible_vgprs: u32

num_cu_per_sh: u32

num_tcc_blocks: u32

gs_vgt_table_depth: u32

gs_prim_buffer_depth: u32

max_gs_waves_per_vgt: u32

pcie_num_lanes: u32

cu_ao_bitmap: [[u32; 4]; 4]

high_va_offset: u64

Starting high virtual address for UMDs.

high_va_max: u64

The maximum high virtual address

pa_sc_tile_steering_override: u32

tcc_disabled_mask: u64

min_engine_clock: u64

min_memory_clock: u64

tcp_cache_size: u32

num_sqc_per_wgp: u32

sqc_data_cache_size: u32

sqc_inst_cache_size: u32

gl1c_cache_size: u32

gl2c_cache_size: u32

mall_size: u64

enabled_rb_pipes_mask_hi: u32

shadow_size: u32

shadow_alignment: u32

csa_size: u32

csa_alignment: u32

Implementations

impl drm_amdgpu_info_device

pub fn get_max_tcc_blocks(&self) -> u32

pub fn get_actual_num_tcc_blocks(&self) -> u32

num_tcc_blocks - self.tcc_disabled_mask.count_ones() = memory channels

pub fn calc_l2_cache_size(&self) -> u32

pub fn calc_l3_cache_size_mb(&self) -> u32

Trait Implementations

impl Clone for drm_amdgpu_info_device

fn clone(&self) -> drm_amdgpu_info_device

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for drm_amdgpu_info_device

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl GPU_INFO for drm_amdgpu_info_device

fn family_id(&self) -> u32

fn chip_external_rev(&self) -> u32

fn device_id(&self) -> u32

fn pci_rev_id(&self) -> u32

fn vram_type(&self) -> u32

fn vram_bit_width(&self) -> u32

Note: AMDGPU driver reports VRAM width per memory channel for LPDDR5 as 64-bits. https://gitlab.freedesktop.org/drm/amd/-/issues/2468

fn max_memory_clock(&self) -> u64

KHz

fn max_engine_clock(&self) -> u64

KHz

fn ids_flags(&self) -> u64

fn rb_pipes(&self) -> u32

fn cu_active_number(&self) -> u32

fn max_se(&self) -> u32

fn max_sa_per_se(&self) -> u32

fn get_family_name(&self) -> FAMILY_NAME

fn get_asic_name(&self) -> ASIC_NAME

fn get_chip_class(&self) -> CHIP_CLASS

fn get_vram_type(&self) -> VRAM_TYPE

fn is_apu(&self) -> bool

fn peak_memory_bw(&self) -> u64

fn peak_memory_bw_gb(&self) -> u64

fn calc_rop_count(&self) -> u32

fn peak_gflops(&self) -> u32

[CU] * [Lane] * 2 [ops] * [GHz]

fn parse_amdgpu_ids(&self) -> String

fn get_max_good_cu_per_sa(&self) -> u32

fn get_min_good_cu_per_sa(&self) -> u32

fn get_l1_cache_size(&self) -> u32

fn get_gl1_cache_size(&self) -> u32

fn get_gfx_target_version(&self) -> Option<GfxTargetVersion>

ref: drivers/gpu/drm/amd/amd/amdkfd/kfd_device.c

impl Copy for drm_amdgpu_info_device