Trait lav::SimdBits[−][src]

pub trait SimdBits<B: Bits, const LANES: usize> where
    Self: Clone + Copy + Default,
    Self: PartialEq + Eq + PartialOrd + Ord,
    Self: From<[B; LANES]> + AsRef<[B; LANES]> + AsMut<[B; LANES]>,
    Self: Product<Self> + Sum<Self>,
    for<'a> Self: Product<&'a Self> + Sum<&'a Self>,
    Self: Hash,
    Self: Debug + Octal,
    Self: Index<usize, Output = B> + IndexMut<usize, Output = B>,
    Self: Select<Self::Mask>,
    Self: Add<Output = Self> + AddAssign,
    Self: Sub<Output = Self> + SubAssign,
    Self: Mul<Output = Self> + MulAssign,
    Self: Div<Output = Self> + DivAssign,
    Self: Rem<Output = Self> + RemAssign,
    Self: Shl<Output = Self> + ShlAssign,
    Self: Shr<Output = Self> + ShrAssign,
    Self: BitAnd<Output = Self> + BitAndAssign,
    Self: BitOr<Output = Self> + BitOrAssign,
    Self: BitXor<Output = Self> + BitXorAssign,
    for<'a> Self: Add<&'a Self, Output = Self> + AddAssign<&'a Self>,
    for<'a> Self: Sub<&'a Self, Output = Self> + SubAssign<&'a Self>,
    for<'a> Self: Mul<&'a Self, Output = Self> + MulAssign<&'a Self>,
    for<'a> Self: Div<&'a Self, Output = Self> + DivAssign<&'a Self>,
    for<'a> Self: Rem<&'a Self, Output = Self> + RemAssign<&'a Self>,
    for<'a> Self: Shl<&'a Self, Output = Self> + ShlAssign<&'a Self>,
    for<'a> Self: Shr<&'a Self, Output = Self> + ShrAssign<&'a Self>,
    for<'a> Self: BitAnd<&'a Self, Output = Self> + BitAndAssign<&'a Self>,
    for<'a> Self: BitOr<&'a Self, Output = Self> + BitOrAssign<&'a Self>,
    for<'a> Self: BitXor<&'a Self, Output = Self> + BitXorAssign<&'a Self>,
    Self: Not<Output = Self>, {
    type Mask: SimdMask<LANES>;

    const LANES: usize;

    fn splat(value: B) -> Self;

    fn lanes_eq(self, other: Self) -> Self::Mask;

    fn lanes_ne(self, other: Self) -> Self::Mask;

    fn lanes_lt(self, other: Self) -> Self::Mask;

    fn lanes_gt(self, other: Self) -> Self::Mask;

    fn lanes_le(self, other: Self) -> Self::Mask;

    fn lanes_ge(self, other: Self) -> Self::Mask;

    fn saturating_add(self, other: Self) -> Self;

    fn saturating_sub(self, other: Self) -> Self;

    fn lanes(&self) -> usize { ... }

    fn abs_sub(self, other: Self) -> Self { ... }
}
Expand description

Bits representation vector of SimdReal vector with associated SimdMask vector.

Associated Types

Associated mask vector.

Associated Constants

Number of lanes in this vector.

Required methods

Constructs a SIMD vector by setting all lanes to the given value.

Test if each lane is equal to the corresponding lane in other.

Test if each lane is not equal to the corresponding lane in other.

Test if each lane is less than the corresponding lane in other.

Test if each lane is greater than the corresponding lane in other.

Test if each lane is less than or equal to the corresponding lane in other.

Test if each lane is greater than or equal to the corresponding lane in other.

Lanewise saturating add.

Lanewise saturating subtract.

Provided methods

Get the number of lanes in this vector.

Lanewise absolute subtract.

Equals self.saturating_sub(other) | other.saturating_sub(self).

Implementations on Foreign Types

Implementors