Struct kea_hal::clocks::ics::SystemClock

pub struct SystemClock<Source, FLL, LowPower> { /* fields omitted */ }

struct that represents the state of the System Clock output ICSOUT

Implementations

impl SystemClock<IntRefClock, FllBypassed, LpEnabled>

In FBILP mode

pub fn into_fbi(self) -> SystemClock<IntRefClock, FllBypassed, LpDisabled>

Can only transition to FBI mode

impl SystemClock<ExtRefClock, FllBypassed, LpEnabled>

In FBELP mode

pub fn into_fbe(self) -> SystemClock<ExtRefClock, FllBypassed, LpDisabled>

Can only transition to FBE mode

impl<Source, Fll> SystemClock<Source, Fll, LpDisabled>

pub fn into_fei(self) -> SystemClock<IntRefClock, FllEnabled, LpDisabled>

Transition from any non-lowpower mode

pub fn into_fbi(self) -> SystemClock<IntRefClock, FllBypassed, LpDisabled>

Transition from any non-lowpower mode

Technically, fbi mode isn’t active until CLKST shows it. It’s up to the caller to decide if they want to wait

pub fn into_fee(self) -> SystemClock<ExtRefClock, FllEnabled, LpDisabled>

Transition from any non-lowpower mode.

pub fn into_fbe(self) -> SystemClock<ExtRefClock, FllBypassed, LpDisabled>

Transition from any non-lowpower mode

Technically, fbe mode isn’t active until CLKST shows it. It’s up to the caller to decide if they want to wait

impl<Source> SystemClock<Source, FllBypassed, LpDisabled>

In FBE or FBI mode, depending on Source

pub fn into_low_power(self) -> SystemClock<Source, FllBypassed, LpEnabled>

Transition to FBELP or FBILP mode, whichever is the low power version of the current mode.

If in FBE mode, calling this method will transition to FBELP. Likewise for FBI and FBILP.

impl<Fll, LowPower> SystemClock<IntRefClock, Fll, LowPower>

Any Internal mode (cannot be set in FEE, FBE, or FBELP mode)

pub fn rdiv(&self, div: u8) -> Result<(), Error>

Set the RDIV value

RDIV divides the output of the external reference clock by powers of 2. RDIV_OUT = OSC_OUT / (2 ** n + 1) The value at reset is 0 (RDIV_OUT = OSC_OUT)

Note that per RDIV definition (pg272 in ICS_C1 of KEA64 ref man) this cannot be changed while the SystemClock is in FEE or FBE mode. To use set this first, then transition to FBE or FEE mode.

impl<Fll, LowPower> SystemClock<ExtRefClock, Fll, LowPower>

Any External mode (cannot be set in FEI, FBI, or FBILP)

pub fn clock_monitor(&self, enable: bool)

Enable/Disable Clock Monitor.

When enabled, the MCU will reset if it loses the external clock signal

impl<Source, Fll, LowPower> SystemClock<Source, Fll, LowPower>

For any state of SystemClock

pub fn set_bdiv(self, div: u8) -> Result<(), Error>

Set the BDIV value

BDIV divides the output of the ICS (in any mode) by powers of 2. ICSOUT = CLKSoutput / (2 ** n + 1) The value at reset is 1 (ICSOUT = CLKSoutput / 2)

Note that by default the bus clock and system clock run at the same multiplier, but the max bus clock is 20MHz. SIM_BUSDIV must be set appropriately to ensure this limit is not exceeded before BDIV is set to 1.

Trait Implementations

impl<Source, FLL, LowPower> Clone for SystemClock<Source, FLL, LowPower>

fn clone(&self) -> SystemClock<Source, FLL, LowPower>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<Source, FLL, LowPower> Copy for SystemClock<Source, FLL, LowPower>