Struct Riscv64InstructionBuilder 

pub struct Riscv64InstructionBuilder { /* private fields */ }

Instruction builder for generating RISC-V instructions

Implementations

impl Riscv64InstructionBuilder

pub fn new() -> Self

pub fn raw_instructions(&self) -> &[Instruction]

Returns a slice of the raw instructions.

This method exposes the internal instruction buffer directly as a slice. Prefer using the instructions() method from the InstructionBuilder trait for most use cases, as it provides a higher-level abstraction and is part of the public API. Use raw_instructions only if you specifically need access to the underlying slice for migration or performance reasons.

pub fn push(&mut self, instr: Instruction) -> &mut Self

pub fn clear(&mut self) -> &mut Self

impl Riscv64InstructionBuilder

pub fn csrrw(&mut self, rd: Register, csr: Csr, rs1: Register) -> &mut Self

Generate CSR read-write instruction

pub fn csrrs(&mut self, rd: Register, csr: Csr, rs1: Register) -> &mut Self

Generate CSR read-set instruction

pub fn csrrc(&mut self, rd: Register, csr: Csr, rs1: Register) -> &mut Self

Generate CSR read-clear instruction

pub fn csrrwi(&mut self, rd: Register, csr: Csr, uimm: u8) -> &mut Self

Generate CSR read-write immediate instruction

pub fn csrrsi(&mut self, rd: Register, csr: Csr, uimm: u8) -> &mut Self

Generate CSR read-set immediate instruction

pub fn csrrci(&mut self, rd: Register, csr: Csr, uimm: u8) -> &mut Self

Generate CSR read-clear immediate instruction

pub fn csrr(&mut self, rd: Register, csr: Csr) -> &mut Self

CSR read (alias for csrrs with rs1=x0) This is a common alias in RISC-V assembly

pub fn csrw(&mut self, csr: Csr, rs1: Register) -> &mut Self

CSR write (alias for csrrw with rd=x0) This is a common alias in RISC-V assembly for writing to CSR without reading old value

pub fn csrs(&mut self, csr: Csr, rs1: Register) -> &mut Self

CSR set (alias for csrrs with rd=x0) This is a common alias in RISC-V assembly for setting bits in CSR without reading old value

pub fn csrc(&mut self, csr: Csr, rs1: Register) -> &mut Self

CSR clear (alias for csrrc with rd=x0) This is a common alias in RISC-V assembly for clearing bits in CSR without reading old value

pub fn csrwi(&mut self, csr: Csr, uimm: u8) -> &mut Self

CSR write immediate (alias for csrrwi with rd=x0) This is a common alias in RISC-V assembly for writing immediate to CSR without reading old value

pub fn csrsi(&mut self, csr: Csr, uimm: u8) -> &mut Self

CSR set immediate (alias for csrrsi with rd=x0) This is a common alias in RISC-V assembly for setting bits in CSR with immediate without reading old value

pub fn csrci(&mut self, csr: Csr, uimm: u8) -> &mut Self

CSR clear immediate (alias for csrrci with rd=x0) This is a common alias in RISC-V assembly for clearing bits in CSR with immediate without reading old value

pub fn add(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate add instruction

pub fn addi(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate add immediate instruction

pub fn sub(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate subtract instruction

pub fn subi(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate subtract immediate instruction

pub fn xor(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate XOR instruction

pub fn xori(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate XOR immediate instruction

pub fn or(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate OR instruction

pub fn ori(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate OR immediate instruction

pub fn slt(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate Set Less Than instruction

pub fn slti(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate Set Less Than immediate instruction

pub fn sltu(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate Set Less Than Unsigned instruction

pub fn sltiu(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate Set Less Than immediate Unsigned instruction

pub fn sll(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate SLL (Shift Left Logical) instruction

pub fn srl(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate SRL (Shift Right Logical) instruction

pub fn sra(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate SRA (Shift Right Arithmetic) instruction

pub fn slli(&mut self, rd: Register, rs1: Register, shamt: u8) -> &mut Self

Generate SLLI (Shift Left Logical Immediate) instruction

pub fn srli(&mut self, rd: Register, rs1: Register, shamt: u8) -> &mut Self

Generate SRLI (Shift Right Logical Immediate) instruction

pub fn srai(&mut self, rd: Register, rs1: Register, shamt: u8) -> &mut Self

Generate SRAI (Shift Right Arithmetic Immediate) instruction

pub fn and(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate AND instruction

pub fn andi(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate AND immediate instruction

pub fn mul(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate MUL (Multiply) instruction Performs signed multiplication and returns the lower 64 bits of the result

pub fn mulh(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate MULH (Multiply High) instruction Performs signed × signed multiplication and returns the upper 64 bits of the result

pub fn mulhsu( &mut self, rd: Register, rs1: Register, rs2: Register, ) -> &mut Self

Generate MULHSU (Multiply High Signed × Unsigned) instruction Performs signed × unsigned multiplication and returns the upper 64 bits of the result

pub fn mulhu(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate MULHU (Multiply High Unsigned) instruction Performs unsigned × unsigned multiplication and returns the upper 64 bits of the result

pub fn div(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate DIV (Divide) instruction Performs signed division: rs1 ÷ rs2

pub fn divu(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate DIVU (Divide Unsigned) instruction Performs unsigned division: rs1 ÷ rs2

pub fn rem(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate REM (Remainder) instruction Computes signed remainder: rs1 % rs2

pub fn remu(&mut self, rd: Register, rs1: Register, rs2: Register) -> &mut Self

Generate REMU (Remainder Unsigned) instruction Computes unsigned remainder: rs1 % rs2

pub fn ld(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LD (Load Doubleword) instruction

pub fn lw(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LW (Load Word) instruction

pub fn lh(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LH (Load Halfword) instruction

pub fn lb(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LB (Load Byte) instruction

pub fn lbu(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LBU (Load Byte Unsigned) instruction

pub fn lhu(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LHU (Load Halfword Unsigned) instruction

pub fn lwu(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate LWU (Load Word Unsigned) instruction

pub fn li(&mut self, rd: Register, imm: i32) -> &mut Self

Load immediate value into register (handles large immediates) This is a common pseudo-instruction in RISC-V assembly

pub fn sd(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate SD (Store Doubleword) instruction

pub fn sw(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate SW (Store Word) instruction

pub fn sh(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate SH (Store Halfword) instruction

pub fn sb(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate SB (Store Byte) instruction

pub fn lui(&mut self, rd: Register, imm: u32) -> &mut Self

Generate LUI (Load Upper Immediate) instruction

pub fn auipc(&mut self, rd: Register, imm: u32) -> &mut Self

Generate AUIPC (Add Upper Immediate to PC) instruction

pub fn jal(&mut self, rd: Register, imm: i32) -> &mut Self

Generate JAL (Jump and Link) instruction

pub fn jalr(&mut self, rd: Register, rs1: Register, imm: i16) -> &mut Self

Generate JALR (Jump and Link Register) instruction

pub fn beq(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BEQ (Branch if Equal) instruction

pub fn bne(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BNE (Branch if Not Equal) instruction

pub fn blt(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BLT (Branch if Less Than) instruction

pub fn bge(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BGE (Branch if Greater or Equal) instruction

pub fn bltu(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BLTU (Branch if Less Than Unsigned) instruction

pub fn bgeu(&mut self, rs1: Register, rs2: Register, imm: i16) -> &mut Self

Generate BGEU (Branch if Greater or Equal Unsigned) instruction

pub fn sret(&mut self) -> &mut Self

Supervisor return instruction Returns from supervisor mode to user mode or previous privilege level This is a privileged instruction that can only be executed in supervisor mode or higher

pub fn mret(&mut self) -> &mut Self

Machine return instruction Returns from machine mode to previous privilege level This is a privileged instruction that can only be executed in machine mode

pub fn ecall(&mut self) -> &mut Self

Environment call instruction Generates a system call to the execution environment

pub fn ebreak(&mut self) -> &mut Self

Environment break instruction Generates a breakpoint exception

pub fn wfi(&mut self) -> &mut Self

Wait for interrupt instruction Puts the processor in a low-power state until an interrupt occurs This is a privileged instruction

pub fn ret(&mut self) -> &mut Self

Return instruction (alias for jalr x0, x1, 0) This is a common alias in RISC-V assembly for returning from a function

Trait Implementations

impl InstructionBuilder<Instruction> for Riscv64InstructionBuilder

unsafe fn function<F>(&self) -> Result<CallableJitFunction<F>, JitError>

Create a JIT-compiled function from the assembled instructions (std-only)

This method converts the assembled instructions into executable machine code that can be called directly as a function. The generic type parameter F specifies the function signature.

Safety

This function is unsafe because:

• It allocates executable memory
• It assumes the assembled code follows the correct ABI
• The caller must ensure the function signature matches the actual code

Examples

use jit_assembler::riscv64::{reg, Riscv64InstructionBuilder};
use jit_assembler::common::InstructionBuilder;
 
let add_func = unsafe {
    Riscv64InstructionBuilder::new()
        .add(reg::A0, reg::A0, reg::A1) // Add first two arguments
        .ret()
        .function::<fn(u64, u64) -> u64>()
}.expect("Failed to create JIT function");
 
// Call the JIT function directly (only works on RISC-V hosts)
let result = add_func.call(10, 20); // Should return 30

type Register = Register

The register type used by this architecture

fn new() -> Self

Create a new instruction builder

fn instructions(&self) -> InstructionCollection<Instruction>

Get the generated instructions

fn push(&mut self, instr: Instruction)

Add an instruction to the builder

fn clear(&mut self)

Clear all instructions

unsafe fn raw_function(&self) -> Result<RawCallableJitFunction, JitError>

Create a raw JIT-compiled function for manual type conversion (std-only)