Struct Aarch64InstructionBuilder 

pub struct Aarch64InstructionBuilder { /* private fields */ }

Instruction builder for generating AArch64 instructions

Implementations

impl Aarch64InstructionBuilder

pub fn new() -> Self

pub fn raw_instructions(&self) -> &[Instruction]

Returns a slice of the raw instructions.

This method exposes the internal instruction buffer directly as a slice. Prefer using the instructions() method from the InstructionBuilder trait for most use cases, as it provides a higher-level abstraction and is part of the public API. Use raw_instructions only if you specifically need access to the underlying slice for migration or performance reasons.

pub fn push(&mut self, instr: Instruction) -> &mut Self

pub fn clear(&mut self) -> &mut Self

pub fn add(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate ADD instruction (64-bit register) ADD Xd, Xn, Xm

pub fn addi(&mut self, rd: Register, rn: Register, imm: u16) -> &mut Self

Generate ADD immediate instruction (64-bit) ADD Xd, Xn, #imm

pub fn sub(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate SUB instruction (64-bit register) SUB Xd, Xn, Xm

pub fn subi(&mut self, rd: Register, rn: Register, imm: u16) -> &mut Self

Generate SUB immediate instruction (64-bit) SUB Xd, Xn, #imm

pub fn mul(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate MUL instruction (64-bit) MUL Xd, Xn, Xm (equivalent to MADD Xd, Xn, Xm, XZR)

pub fn msub( &mut self, rd: Register, rn: Register, rm: Register, ra: Register, ) -> &mut Self

Generate MSUB instruction (64-bit multiply-subtract) MSUB Xd, Xn, Xm, Xa -> Xd = Xa - (Xn * Xm)

pub fn udiv(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate UDIV instruction (64-bit unsigned division) UDIV Xd, Xn, Xm

pub fn sdiv(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate SDIV instruction (64-bit signed division) SDIV Xd, Xn, Xm

pub fn or(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate ORR instruction (logical OR, 64-bit) ORR Xd, Xn, Xm

pub fn and(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate AND instruction (logical AND, 64-bit) AND Xd, Xn, Xm

pub fn xor(&mut self, rd: Register, rn: Register, rm: Register) -> &mut Self

Generate EOR instruction (logical XOR, 64-bit) EOR Xd, Xn, Xm

pub fn mov(&mut self, rd: Register, rm: Register) -> &mut Self

Generate MOV instruction (move register to register) MOV Xd, Xm (implemented as ORR Xd, XZR, Xm)

pub fn ret(&mut self) -> &mut Self

Generate RET instruction (return) RET (returns to X30/LR by default)

pub fn ret_reg(&mut self, rn: Register) -> &mut Self

Generate RET instruction with specific register RET Xn

pub fn movz(&mut self, rd: Register, imm16: u16, shift: u8) -> &mut Self

Generate MOVZ instruction (Move with Zero) MOVZ Xd, #imm16, LSL #(shift*16)

pub fn movk(&mut self, rd: Register, imm16: u16, shift: u8) -> &mut Self

Generate MOVK instruction (Move with Keep) MOVK Xd, #imm16, LSL #(shift*16)

pub fn mov_imm(&mut self, rd: Register, imm: u64) -> &mut Self

Generate immediate move instruction using MOVZ/MOVK for efficient 64-bit loads

pub fn shl(&mut self, rd: Register, rn: Register, shift: u8) -> &mut Self

Generate left shift instruction (using multiply by power of 2) This is a simplified implementation - real AArch64 has LSL instruction

Trait Implementations

impl InstructionBuilder<Instruction> for Aarch64InstructionBuilder

unsafe fn function<F>(&self) -> Result<CallableJitFunction<F>, JitError>

Create a JIT-compiled function from the assembled instructions (std-only)

This method converts the assembled instructions into executable machine code that can be called directly as a function. The generic type parameter F specifies the function signature.

Safety

This function is unsafe because:

• It allocates executable memory
• It assumes the assembled code follows the correct ABI
• The caller must ensure the function signature matches the actual code

Examples

use jit_assembler::aarch64::{reg, Aarch64InstructionBuilder};
use jit_assembler::common::InstructionBuilder;
 
let add_func = unsafe {
    Aarch64InstructionBuilder::new()
        .add(reg::X0, reg::X0, reg::X1) // Add first two arguments
        .ret()
        .function::<fn(u64, u64) -> u64>()
}.expect("Failed to create JIT function");
 
// Call the JIT function directly (only works on AArch64 hosts)
// let result = add_func.call(10, 20); // Returns 30

type Register = Register

The register type used by this architecture

fn new() -> Self

Create a new instruction builder

fn instructions(&self) -> InstructionCollection<Instruction>

Get the generated instructions

fn push(&mut self, instr: Instruction)

Add an instruction to the builder

fn clear(&mut self)

Clear all instructions

unsafe fn raw_function(&self) -> Result<RawCallableJitFunction, JitError>

Create a raw JIT-compiled function for manual type conversion (std-only)