List of all items

Structs

• aarch64::builder::Aarch64InstructionBuilder
• aarch64::instruction::Instruction
• aarch64::instruction::Register
• common::InstructionCollection
• common::jit::CallableJitFunction
• common::jit::RawCallableJitFunction
• riscv64::builder::Riscv64InstructionBuilder
• riscv64::instruction::Csr
• riscv64::instruction::Register

Enums

• common::AbiClass
• common::BuildError
• common::jit::JitError
• riscv64::instruction::Instruction

Traits

• common::ArchitectureEncoder
• common::Instruction
• common::InstructionBuilder
• common::InstructionCollectionExt
• common::Register

Macros

• aarch64_asm
• jit_asm_generic
• riscv64_asm

Functions

• aarch64::instruction::encode_add_sub_imm
• aarch64::instruction::encode_add_sub_reg
• aarch64::instruction::encode_branch_reg
• aarch64::instruction::encode_divide
• aarch64::instruction::encode_logical_reg
• aarch64::instruction::encode_move_reg
• aarch64::instruction::encode_movk
• aarch64::instruction::encode_movz
• aarch64::instruction::encode_multiply
• aarch64::instruction::encode_ret
• common::instructions_to_bytes
• common::instructions_total_size
• riscv64::instruction::encode_b_type
• riscv64::instruction::encode_csr_imm_type
• riscv64::instruction::encode_csr_type
• riscv64::instruction::encode_i_type
• riscv64::instruction::encode_j_type
• riscv64::instruction::encode_privileged_type
• riscv64::instruction::encode_r_type
• riscv64::instruction::encode_s_type
• riscv64::instruction::encode_u_type

Type Aliases

• common::BuildResult

Constants

• aarch64::instruction::reg::FP
• aarch64::instruction::reg::LR
• aarch64::instruction::reg::SP
• aarch64::instruction::reg::WZR
• aarch64::instruction::reg::X0
• aarch64::instruction::reg::X1
• aarch64::instruction::reg::X10
• aarch64::instruction::reg::X11
• aarch64::instruction::reg::X12
• aarch64::instruction::reg::X13
• aarch64::instruction::reg::X14
• aarch64::instruction::reg::X15
• aarch64::instruction::reg::X16
• aarch64::instruction::reg::X17
• aarch64::instruction::reg::X18
• aarch64::instruction::reg::X19
• aarch64::instruction::reg::X2
• aarch64::instruction::reg::X20
• aarch64::instruction::reg::X21
• aarch64::instruction::reg::X22
• aarch64::instruction::reg::X23
• aarch64::instruction::reg::X24
• aarch64::instruction::reg::X25
• aarch64::instruction::reg::X26
• aarch64::instruction::reg::X27
• aarch64::instruction::reg::X28
• aarch64::instruction::reg::X29
• aarch64::instruction::reg::X3
• aarch64::instruction::reg::X30
• aarch64::instruction::reg::X4
• aarch64::instruction::reg::X5
• aarch64::instruction::reg::X6
• aarch64::instruction::reg::X7
• aarch64::instruction::reg::X8
• aarch64::instruction::reg::X9
• aarch64::instruction::reg::XZR
• riscv64::instruction::alu_funct3::ADD_SUB
• riscv64::instruction::alu_funct3::AND
• riscv64::instruction::alu_funct3::OR
• riscv64::instruction::alu_funct3::SLL
• riscv64::instruction::alu_funct3::SLT
• riscv64::instruction::alu_funct3::SLTU
• riscv64::instruction::alu_funct3::SRL_SRA
• riscv64::instruction::alu_funct3::XOR
• riscv64::instruction::branch_funct3::BEQ
• riscv64::instruction::branch_funct3::BGE
• riscv64::instruction::branch_funct3::BGEU
• riscv64::instruction::branch_funct3::BLT
• riscv64::instruction::branch_funct3::BLTU
• riscv64::instruction::branch_funct3::BNE
• riscv64::instruction::csr::MCAUSE
• riscv64::instruction::csr::MEDELEG
• riscv64::instruction::csr::MEPC
• riscv64::instruction::csr::MHARTID
• riscv64::instruction::csr::MIDELEG
• riscv64::instruction::csr::MIE
• riscv64::instruction::csr::MIP
• riscv64::instruction::csr::MISA
• riscv64::instruction::csr::MSCRATCH
• riscv64::instruction::csr::MSTATUS
• riscv64::instruction::csr::MTVAL
• riscv64::instruction::csr::MTVEC
• riscv64::instruction::csr::SCAUSE
• riscv64::instruction::csr::SEPC
• riscv64::instruction::csr::SIE
• riscv64::instruction::csr::SIP
• riscv64::instruction::csr::SSCRATCH
• riscv64::instruction::csr::SSTATUS
• riscv64::instruction::csr::STVAL
• riscv64::instruction::csr::STVEC
• riscv64::instruction::load_funct3::LB
• riscv64::instruction::load_funct3::LBU
• riscv64::instruction::load_funct3::LD
• riscv64::instruction::load_funct3::LH
• riscv64::instruction::load_funct3::LHU
• riscv64::instruction::load_funct3::LW
• riscv64::instruction::load_funct3::LWU
• riscv64::instruction::m_funct3::DIV
• riscv64::instruction::m_funct3::DIVU
• riscv64::instruction::m_funct3::MUL
• riscv64::instruction::m_funct3::MULH
• riscv64::instruction::m_funct3::MULHSU
• riscv64::instruction::m_funct3::MULHU
• riscv64::instruction::m_funct3::REM
• riscv64::instruction::m_funct3::REMU
• riscv64::instruction::m_funct7::M_EXT
• riscv64::instruction::opcodes::AUIPC
• riscv64::instruction::opcodes::BRANCH
• riscv64::instruction::opcodes::JAL
• riscv64::instruction::opcodes::JALR
• riscv64::instruction::opcodes::LOAD
• riscv64::instruction::opcodes::LUI
• riscv64::instruction::opcodes::OP
• riscv64::instruction::opcodes::OP_32
• riscv64::instruction::opcodes::OP_IMM
• riscv64::instruction::opcodes::OP_IMM_32
• riscv64::instruction::opcodes::STORE
• riscv64::instruction::opcodes::SYSTEM
• riscv64::instruction::privileged_funct12::EBREAK
• riscv64::instruction::privileged_funct12::ECALL
• riscv64::instruction::privileged_funct12::MRET
• riscv64::instruction::privileged_funct12::SRET
• riscv64::instruction::privileged_funct12::WFI
• riscv64::instruction::reg::A0
• riscv64::instruction::reg::A1
• riscv64::instruction::reg::A2
• riscv64::instruction::reg::A3
• riscv64::instruction::reg::A4
• riscv64::instruction::reg::A5
• riscv64::instruction::reg::A6
• riscv64::instruction::reg::A7
• riscv64::instruction::reg::FP
• riscv64::instruction::reg::GP
• riscv64::instruction::reg::RA
• riscv64::instruction::reg::S0
• riscv64::instruction::reg::S1
• riscv64::instruction::reg::S10
• riscv64::instruction::reg::S11
• riscv64::instruction::reg::S2
• riscv64::instruction::reg::S3
• riscv64::instruction::reg::S4
• riscv64::instruction::reg::S5
• riscv64::instruction::reg::S6
• riscv64::instruction::reg::S7
• riscv64::instruction::reg::S8
• riscv64::instruction::reg::S9
• riscv64::instruction::reg::SP
• riscv64::instruction::reg::T0
• riscv64::instruction::reg::T1
• riscv64::instruction::reg::T2
• riscv64::instruction::reg::T3
• riscv64::instruction::reg::T4
• riscv64::instruction::reg::T5
• riscv64::instruction::reg::T6
• riscv64::instruction::reg::TP
• riscv64::instruction::reg::X0
• riscv64::instruction::reg::X1
• riscv64::instruction::reg::X10
• riscv64::instruction::reg::X11
• riscv64::instruction::reg::X12
• riscv64::instruction::reg::X13
• riscv64::instruction::reg::X14
• riscv64::instruction::reg::X15
• riscv64::instruction::reg::X16
• riscv64::instruction::reg::X17
• riscv64::instruction::reg::X18
• riscv64::instruction::reg::X19
• riscv64::instruction::reg::X2
• riscv64::instruction::reg::X20
• riscv64::instruction::reg::X21
• riscv64::instruction::reg::X22
• riscv64::instruction::reg::X23
• riscv64::instruction::reg::X24
• riscv64::instruction::reg::X25
• riscv64::instruction::reg::X26
• riscv64::instruction::reg::X27
• riscv64::instruction::reg::X28
• riscv64::instruction::reg::X29
• riscv64::instruction::reg::X3
• riscv64::instruction::reg::X30
• riscv64::instruction::reg::X31
• riscv64::instruction::reg::X4
• riscv64::instruction::reg::X5
• riscv64::instruction::reg::X6
• riscv64::instruction::reg::X7
• riscv64::instruction::reg::X8
• riscv64::instruction::reg::X9
• riscv64::instruction::reg::ZERO
• riscv64::instruction::store_funct3::SB
• riscv64::instruction::store_funct3::SD
• riscv64::instruction::store_funct3::SH
• riscv64::instruction::store_funct3::SW
• riscv64::instruction::system_funct3::CSRRC
• riscv64::instruction::system_funct3::CSRRCI
• riscv64::instruction::system_funct3::CSRRS
• riscv64::instruction::system_funct3::CSRRSI
• riscv64::instruction::system_funct3::CSRRW
• riscv64::instruction::system_funct3::CSRRWI