encode_add_sub_reg

jit_assembler::aarch64::instruction

Function encode_add_sub_reg 

Source 
pub fn encode_add_sub_reg(
    sf: u8,
    op: u8,
    s: u8,
    rm: Register,
    imm6: u8,
    rn: Register,
    rd: Register,
) -> Instruction
Expand description

Data Processing - Register instruction encoding (3-operand)