List of all items
Structs
- R
- Reg
- RegisterBlock
- W
- lowpwr_ctrl::CPU_PWRGATE_W
- lowpwr_ctrl::DISPLAY_PWRGATE_W
- lowpwr_ctrl::GPU_PWRGATE_W
- lowpwr_ctrl::L1_PWRGATE_W
- lowpwr_ctrl::L2_PWRGATE_W
- lowpwr_ctrl::LPBG_SEL_W
- lowpwr_ctrl::LPBG_TEST_W
- lowpwr_ctrl::MIX_PWRGATE_W
- lowpwr_ctrl::OSC_SEL_W
- lowpwr_ctrl::RCOSC_CG_OVERRIDE_W
- lowpwr_ctrl::RC_OSC_EN_W
- lowpwr_ctrl::REFTOP_IBIAS_OFF_W
- lowpwr_ctrl::XTALOSC_PWRUP_DELAY_W
- lowpwr_ctrl_clr::CPU_PWRGATE_W
- lowpwr_ctrl_clr::DISPLAY_PWRGATE_W
- lowpwr_ctrl_clr::GPU_PWRGATE_W
- lowpwr_ctrl_clr::L1_PWRGATE_W
- lowpwr_ctrl_clr::L2_PWRGATE_W
- lowpwr_ctrl_clr::LPBG_SEL_W
- lowpwr_ctrl_clr::LPBG_TEST_W
- lowpwr_ctrl_clr::MIX_PWRGATE_W
- lowpwr_ctrl_clr::OSC_SEL_W
- lowpwr_ctrl_clr::RCOSC_CG_OVERRIDE_W
- lowpwr_ctrl_clr::RC_OSC_EN_W
- lowpwr_ctrl_clr::REFTOP_IBIAS_OFF_W
- lowpwr_ctrl_clr::XTALOSC_PWRUP_DELAY_W
- lowpwr_ctrl_set::CPU_PWRGATE_W
- lowpwr_ctrl_set::DISPLAY_PWRGATE_W
- lowpwr_ctrl_set::GPU_PWRGATE_W
- lowpwr_ctrl_set::L1_PWRGATE_W
- lowpwr_ctrl_set::L2_PWRGATE_W
- lowpwr_ctrl_set::LPBG_SEL_W
- lowpwr_ctrl_set::LPBG_TEST_W
- lowpwr_ctrl_set::MIX_PWRGATE_W
- lowpwr_ctrl_set::OSC_SEL_W
- lowpwr_ctrl_set::RCOSC_CG_OVERRIDE_W
- lowpwr_ctrl_set::RC_OSC_EN_W
- lowpwr_ctrl_set::REFTOP_IBIAS_OFF_W
- lowpwr_ctrl_set::XTALOSC_PWRUP_DELAY_W
- lowpwr_ctrl_tog::CPU_PWRGATE_W
- lowpwr_ctrl_tog::DISPLAY_PWRGATE_W
- lowpwr_ctrl_tog::GPU_PWRGATE_W
- lowpwr_ctrl_tog::L1_PWRGATE_W
- lowpwr_ctrl_tog::L2_PWRGATE_W
- lowpwr_ctrl_tog::LPBG_SEL_W
- lowpwr_ctrl_tog::LPBG_TEST_W
- lowpwr_ctrl_tog::MIX_PWRGATE_W
- lowpwr_ctrl_tog::OSC_SEL_W
- lowpwr_ctrl_tog::RCOSC_CG_OVERRIDE_W
- lowpwr_ctrl_tog::RC_OSC_EN_W
- lowpwr_ctrl_tog::REFTOP_IBIAS_OFF_W
- lowpwr_ctrl_tog::XTALOSC_PWRUP_DELAY_W
- misc0::CLKGATE_CTRL_W
- misc0::CLKGATE_DELAY_W
- misc0::DISCON_HIGH_SNVS_W
- misc0::OSC_I_W
- misc0::OSC_XTALOK_EN_W
- misc0::REFTOP_PWD_W
- misc0::REFTOP_SELFBIASOFF_W
- misc0::REFTOP_VBGADJ_W
- misc0::REFTOP_VBGUP_W
- misc0::STOP_MODE_CONFIG_W
- misc0::VID_PLL_PREDIV_W
- misc0::XTAL_24M_PWD_W
- misc0_clr::CLKGATE_CTRL_W
- misc0_clr::CLKGATE_DELAY_W
- misc0_clr::DISCON_HIGH_SNVS_W
- misc0_clr::OSC_I_W
- misc0_clr::OSC_XTALOK_EN_W
- misc0_clr::REFTOP_PWD_W
- misc0_clr::REFTOP_SELFBIASOFF_W
- misc0_clr::REFTOP_VBGADJ_W
- misc0_clr::REFTOP_VBGUP_W
- misc0_clr::STOP_MODE_CONFIG_W
- misc0_clr::VID_PLL_PREDIV_W
- misc0_clr::XTAL_24M_PWD_W
- misc0_set::CLKGATE_CTRL_W
- misc0_set::CLKGATE_DELAY_W
- misc0_set::DISCON_HIGH_SNVS_W
- misc0_set::OSC_I_W
- misc0_set::OSC_XTALOK_EN_W
- misc0_set::REFTOP_PWD_W
- misc0_set::REFTOP_SELFBIASOFF_W
- misc0_set::REFTOP_VBGADJ_W
- misc0_set::REFTOP_VBGUP_W
- misc0_set::STOP_MODE_CONFIG_W
- misc0_set::VID_PLL_PREDIV_W
- misc0_set::XTAL_24M_PWD_W
- misc0_tog::CLKGATE_CTRL_W
- misc0_tog::CLKGATE_DELAY_W
- misc0_tog::DISCON_HIGH_SNVS_W
- misc0_tog::OSC_I_W
- misc0_tog::OSC_XTALOK_EN_W
- misc0_tog::REFTOP_PWD_W
- misc0_tog::REFTOP_SELFBIASOFF_W
- misc0_tog::REFTOP_VBGADJ_W
- misc0_tog::REFTOP_VBGUP_W
- misc0_tog::STOP_MODE_CONFIG_W
- misc0_tog::VID_PLL_PREDIV_W
- misc0_tog::XTAL_24M_PWD_W
- osc_config0::BYPASS_W
- osc_config0::ENABLE_W
- osc_config0::HYST_MINUS_W
- osc_config0::HYST_PLUS_W
- osc_config0::INVERT_W
- osc_config0::RC_OSC_PROG_CUR_W
- osc_config0::RC_OSC_PROG_W
- osc_config0::START_W
- osc_config0_clr::BYPASS_W
- osc_config0_clr::ENABLE_W
- osc_config0_clr::HYST_MINUS_W
- osc_config0_clr::HYST_PLUS_W
- osc_config0_clr::INVERT_W
- osc_config0_clr::RC_OSC_PROG_CUR_W
- osc_config0_clr::RC_OSC_PROG_W
- osc_config0_clr::START_W
- osc_config0_set::BYPASS_W
- osc_config0_set::ENABLE_W
- osc_config0_set::HYST_MINUS_W
- osc_config0_set::HYST_PLUS_W
- osc_config0_set::INVERT_W
- osc_config0_set::RC_OSC_PROG_CUR_W
- osc_config0_set::RC_OSC_PROG_W
- osc_config0_set::START_W
- osc_config0_tog::BYPASS_W
- osc_config0_tog::ENABLE_W
- osc_config0_tog::HYST_MINUS_W
- osc_config0_tog::HYST_PLUS_W
- osc_config0_tog::INVERT_W
- osc_config0_tog::RC_OSC_PROG_CUR_W
- osc_config0_tog::RC_OSC_PROG_W
- osc_config0_tog::START_W
- osc_config1::COUNT_RC_CUR_W
- osc_config1::COUNT_RC_TRG_W
- osc_config1_clr::COUNT_RC_CUR_W
- osc_config1_clr::COUNT_RC_TRG_W
- osc_config1_set::COUNT_RC_CUR_W
- osc_config1_set::COUNT_RC_TRG_W
- osc_config1_tog::COUNT_RC_CUR_W
- osc_config1_tog::COUNT_RC_TRG_W
- osc_config2::CLK_1M_ERR_FL_W
- osc_config2::COUNT_1M_TRG_W
- osc_config2::ENABLE_1M_W
- osc_config2::MUX_1M_W
- osc_config2_clr::CLK_1M_ERR_FL_W
- osc_config2_clr::COUNT_1M_TRG_W
- osc_config2_clr::ENABLE_1M_W
- osc_config2_clr::MUX_1M_W
- osc_config2_set::CLK_1M_ERR_FL_W
- osc_config2_set::COUNT_1M_TRG_W
- osc_config2_set::ENABLE_1M_W
- osc_config2_set::MUX_1M_W
- osc_config2_tog::CLK_1M_ERR_FL_W
- osc_config2_tog::COUNT_1M_TRG_W
- osc_config2_tog::ENABLE_1M_W
- osc_config2_tog::MUX_1M_W
Enums
- Variant
- lowpwr_ctrl::LPBG_SEL_A
- lowpwr_ctrl::OSC_SEL_A
- lowpwr_ctrl::RC_OSC_EN_A
- lowpwr_ctrl::XTALOSC_PWRUP_DELAY_A
- lowpwr_ctrl::XTALOSC_PWRUP_STAT_A
- lowpwr_ctrl_clr::LPBG_SEL_A
- lowpwr_ctrl_clr::OSC_SEL_A
- lowpwr_ctrl_clr::RC_OSC_EN_A
- lowpwr_ctrl_clr::XTALOSC_PWRUP_DELAY_A
- lowpwr_ctrl_clr::XTALOSC_PWRUP_STAT_A
- lowpwr_ctrl_set::LPBG_SEL_A
- lowpwr_ctrl_set::OSC_SEL_A
- lowpwr_ctrl_set::RC_OSC_EN_A
- lowpwr_ctrl_set::XTALOSC_PWRUP_DELAY_A
- lowpwr_ctrl_set::XTALOSC_PWRUP_STAT_A
- lowpwr_ctrl_tog::LPBG_SEL_A
- lowpwr_ctrl_tog::OSC_SEL_A
- lowpwr_ctrl_tog::RC_OSC_EN_A
- lowpwr_ctrl_tog::XTALOSC_PWRUP_DELAY_A
- lowpwr_ctrl_tog::XTALOSC_PWRUP_STAT_A
- misc0::CLKGATE_CTRL_A
- misc0::CLKGATE_DELAY_A
- misc0::DISCON_HIGH_SNVS_A
- misc0::OSC_I_A
- misc0::REFTOP_SELFBIASOFF_A
- misc0::REFTOP_VBGADJ_A
- misc0::RTC_XTAL_SOURCE_A
- misc0::STOP_MODE_CONFIG_A
- misc0::VID_PLL_PREDIV_A
- misc0_clr::CLKGATE_CTRL_A
- misc0_clr::CLKGATE_DELAY_A
- misc0_clr::DISCON_HIGH_SNVS_A
- misc0_clr::OSC_I_A
- misc0_clr::REFTOP_SELFBIASOFF_A
- misc0_clr::REFTOP_VBGADJ_A
- misc0_clr::RTC_XTAL_SOURCE_A
- misc0_clr::STOP_MODE_CONFIG_A
- misc0_clr::VID_PLL_PREDIV_A
- misc0_set::CLKGATE_CTRL_A
- misc0_set::CLKGATE_DELAY_A
- misc0_set::DISCON_HIGH_SNVS_A
- misc0_set::OSC_I_A
- misc0_set::REFTOP_SELFBIASOFF_A
- misc0_set::REFTOP_VBGADJ_A
- misc0_set::RTC_XTAL_SOURCE_A
- misc0_set::STOP_MODE_CONFIG_A
- misc0_set::VID_PLL_PREDIV_A
- misc0_tog::CLKGATE_CTRL_A
- misc0_tog::CLKGATE_DELAY_A
- misc0_tog::DISCON_HIGH_SNVS_A
- misc0_tog::OSC_I_A
- misc0_tog::REFTOP_SELFBIASOFF_A
- misc0_tog::REFTOP_VBGADJ_A
- misc0_tog::RTC_XTAL_SOURCE_A
- misc0_tog::STOP_MODE_CONFIG_A
- misc0_tog::VID_PLL_PREDIV_A
Traits
Type Aliases
- LOWPWR_CTRL
- LOWPWR_CTRL_CLR
- LOWPWR_CTRL_SET
- LOWPWR_CTRL_TOG
- MISC0
- MISC0_CLR
- MISC0_SET
- MISC0_TOG
- OSC_CONFIG0
- OSC_CONFIG0_CLR
- OSC_CONFIG0_SET
- OSC_CONFIG0_TOG
- OSC_CONFIG1
- OSC_CONFIG1_CLR
- OSC_CONFIG1_SET
- OSC_CONFIG1_TOG
- OSC_CONFIG2
- OSC_CONFIG2_CLR
- OSC_CONFIG2_SET
- OSC_CONFIG2_TOG
- lowpwr_ctrl::CPU_PWRGATE_R
- lowpwr_ctrl::DISPLAY_PWRGATE_R
- lowpwr_ctrl::GPU_PWRGATE_R
- lowpwr_ctrl::L1_PWRGATE_R
- lowpwr_ctrl::L2_PWRGATE_R
- lowpwr_ctrl::LPBG_SEL_R
- lowpwr_ctrl::LPBG_TEST_R
- lowpwr_ctrl::MIX_PWRGATE_R
- lowpwr_ctrl::OSC_SEL_R
- lowpwr_ctrl::R
- lowpwr_ctrl::RCOSC_CG_OVERRIDE_R
- lowpwr_ctrl::RC_OSC_EN_R
- lowpwr_ctrl::REFTOP_IBIAS_OFF_R
- lowpwr_ctrl::W
- lowpwr_ctrl::XTALOSC_PWRUP_DELAY_R
- lowpwr_ctrl::XTALOSC_PWRUP_STAT_R
- lowpwr_ctrl_clr::CPU_PWRGATE_R
- lowpwr_ctrl_clr::DISPLAY_PWRGATE_R
- lowpwr_ctrl_clr::GPU_PWRGATE_R
- lowpwr_ctrl_clr::L1_PWRGATE_R
- lowpwr_ctrl_clr::L2_PWRGATE_R
- lowpwr_ctrl_clr::LPBG_SEL_R
- lowpwr_ctrl_clr::LPBG_TEST_R
- lowpwr_ctrl_clr::MIX_PWRGATE_R
- lowpwr_ctrl_clr::OSC_SEL_R
- lowpwr_ctrl_clr::R
- lowpwr_ctrl_clr::RCOSC_CG_OVERRIDE_R
- lowpwr_ctrl_clr::RC_OSC_EN_R
- lowpwr_ctrl_clr::REFTOP_IBIAS_OFF_R
- lowpwr_ctrl_clr::W
- lowpwr_ctrl_clr::XTALOSC_PWRUP_DELAY_R
- lowpwr_ctrl_clr::XTALOSC_PWRUP_STAT_R
- lowpwr_ctrl_set::CPU_PWRGATE_R
- lowpwr_ctrl_set::DISPLAY_PWRGATE_R
- lowpwr_ctrl_set::GPU_PWRGATE_R
- lowpwr_ctrl_set::L1_PWRGATE_R
- lowpwr_ctrl_set::L2_PWRGATE_R
- lowpwr_ctrl_set::LPBG_SEL_R
- lowpwr_ctrl_set::LPBG_TEST_R
- lowpwr_ctrl_set::MIX_PWRGATE_R
- lowpwr_ctrl_set::OSC_SEL_R
- lowpwr_ctrl_set::R
- lowpwr_ctrl_set::RCOSC_CG_OVERRIDE_R
- lowpwr_ctrl_set::RC_OSC_EN_R
- lowpwr_ctrl_set::REFTOP_IBIAS_OFF_R
- lowpwr_ctrl_set::W
- lowpwr_ctrl_set::XTALOSC_PWRUP_DELAY_R
- lowpwr_ctrl_set::XTALOSC_PWRUP_STAT_R
- lowpwr_ctrl_tog::CPU_PWRGATE_R
- lowpwr_ctrl_tog::DISPLAY_PWRGATE_R
- lowpwr_ctrl_tog::GPU_PWRGATE_R
- lowpwr_ctrl_tog::L1_PWRGATE_R
- lowpwr_ctrl_tog::L2_PWRGATE_R
- lowpwr_ctrl_tog::LPBG_SEL_R
- lowpwr_ctrl_tog::LPBG_TEST_R
- lowpwr_ctrl_tog::MIX_PWRGATE_R
- lowpwr_ctrl_tog::OSC_SEL_R
- lowpwr_ctrl_tog::R
- lowpwr_ctrl_tog::RCOSC_CG_OVERRIDE_R
- lowpwr_ctrl_tog::RC_OSC_EN_R
- lowpwr_ctrl_tog::REFTOP_IBIAS_OFF_R
- lowpwr_ctrl_tog::W
- lowpwr_ctrl_tog::XTALOSC_PWRUP_DELAY_R
- lowpwr_ctrl_tog::XTALOSC_PWRUP_STAT_R
- misc0::CLKGATE_CTRL_R
- misc0::CLKGATE_DELAY_R
- misc0::DISCON_HIGH_SNVS_R
- misc0::OSC_I_R
- misc0::OSC_XTALOK_EN_R
- misc0::OSC_XTALOK_R
- misc0::R
- misc0::REFTOP_PWD_R
- misc0::REFTOP_SELFBIASOFF_R
- misc0::REFTOP_VBGADJ_R
- misc0::REFTOP_VBGUP_R
- misc0::RTC_XTAL_SOURCE_R
- misc0::STOP_MODE_CONFIG_R
- misc0::VID_PLL_PREDIV_R
- misc0::W
- misc0::XTAL_24M_PWD_R
- misc0_clr::CLKGATE_CTRL_R
- misc0_clr::CLKGATE_DELAY_R
- misc0_clr::DISCON_HIGH_SNVS_R
- misc0_clr::OSC_I_R
- misc0_clr::OSC_XTALOK_EN_R
- misc0_clr::OSC_XTALOK_R
- misc0_clr::R
- misc0_clr::REFTOP_PWD_R
- misc0_clr::REFTOP_SELFBIASOFF_R
- misc0_clr::REFTOP_VBGADJ_R
- misc0_clr::REFTOP_VBGUP_R
- misc0_clr::RTC_XTAL_SOURCE_R
- misc0_clr::STOP_MODE_CONFIG_R
- misc0_clr::VID_PLL_PREDIV_R
- misc0_clr::W
- misc0_clr::XTAL_24M_PWD_R
- misc0_set::CLKGATE_CTRL_R
- misc0_set::CLKGATE_DELAY_R
- misc0_set::DISCON_HIGH_SNVS_R
- misc0_set::OSC_I_R
- misc0_set::OSC_XTALOK_EN_R
- misc0_set::OSC_XTALOK_R
- misc0_set::R
- misc0_set::REFTOP_PWD_R
- misc0_set::REFTOP_SELFBIASOFF_R
- misc0_set::REFTOP_VBGADJ_R
- misc0_set::REFTOP_VBGUP_R
- misc0_set::RTC_XTAL_SOURCE_R
- misc0_set::STOP_MODE_CONFIG_R
- misc0_set::VID_PLL_PREDIV_R
- misc0_set::W
- misc0_set::XTAL_24M_PWD_R
- misc0_tog::CLKGATE_CTRL_R
- misc0_tog::CLKGATE_DELAY_R
- misc0_tog::DISCON_HIGH_SNVS_R
- misc0_tog::OSC_I_R
- misc0_tog::OSC_XTALOK_EN_R
- misc0_tog::OSC_XTALOK_R
- misc0_tog::R
- misc0_tog::REFTOP_PWD_R
- misc0_tog::REFTOP_SELFBIASOFF_R
- misc0_tog::REFTOP_VBGADJ_R
- misc0_tog::REFTOP_VBGUP_R
- misc0_tog::RTC_XTAL_SOURCE_R
- misc0_tog::STOP_MODE_CONFIG_R
- misc0_tog::VID_PLL_PREDIV_R
- misc0_tog::W
- misc0_tog::XTAL_24M_PWD_R
- osc_config0::BYPASS_R
- osc_config0::ENABLE_R
- osc_config0::HYST_MINUS_R
- osc_config0::HYST_PLUS_R
- osc_config0::INVERT_R
- osc_config0::R
- osc_config0::RC_OSC_PROG_CUR_R
- osc_config0::RC_OSC_PROG_R
- osc_config0::START_R
- osc_config0::W
- osc_config0_clr::BYPASS_R
- osc_config0_clr::ENABLE_R
- osc_config0_clr::HYST_MINUS_R
- osc_config0_clr::HYST_PLUS_R
- osc_config0_clr::INVERT_R
- osc_config0_clr::R
- osc_config0_clr::RC_OSC_PROG_CUR_R
- osc_config0_clr::RC_OSC_PROG_R
- osc_config0_clr::START_R
- osc_config0_clr::W
- osc_config0_set::BYPASS_R
- osc_config0_set::ENABLE_R
- osc_config0_set::HYST_MINUS_R
- osc_config0_set::HYST_PLUS_R
- osc_config0_set::INVERT_R
- osc_config0_set::R
- osc_config0_set::RC_OSC_PROG_CUR_R
- osc_config0_set::RC_OSC_PROG_R
- osc_config0_set::START_R
- osc_config0_set::W
- osc_config0_tog::BYPASS_R
- osc_config0_tog::ENABLE_R
- osc_config0_tog::HYST_MINUS_R
- osc_config0_tog::HYST_PLUS_R
- osc_config0_tog::INVERT_R
- osc_config0_tog::R
- osc_config0_tog::RC_OSC_PROG_CUR_R
- osc_config0_tog::RC_OSC_PROG_R
- osc_config0_tog::START_R
- osc_config0_tog::W
- osc_config1::COUNT_RC_CUR_R
- osc_config1::COUNT_RC_TRG_R
- osc_config1::R
- osc_config1::W
- osc_config1_clr::COUNT_RC_CUR_R
- osc_config1_clr::COUNT_RC_TRG_R
- osc_config1_clr::R
- osc_config1_clr::W
- osc_config1_set::COUNT_RC_CUR_R
- osc_config1_set::COUNT_RC_TRG_R
- osc_config1_set::R
- osc_config1_set::W
- osc_config1_tog::COUNT_RC_CUR_R
- osc_config1_tog::COUNT_RC_TRG_R
- osc_config1_tog::R
- osc_config1_tog::W
- osc_config2::CLK_1M_ERR_FL_R
- osc_config2::COUNT_1M_TRG_R
- osc_config2::ENABLE_1M_R
- osc_config2::MUX_1M_R
- osc_config2::R
- osc_config2::W
- osc_config2_clr::CLK_1M_ERR_FL_R
- osc_config2_clr::COUNT_1M_TRG_R
- osc_config2_clr::ENABLE_1M_R
- osc_config2_clr::MUX_1M_R
- osc_config2_clr::R
- osc_config2_clr::W
- osc_config2_set::CLK_1M_ERR_FL_R
- osc_config2_set::COUNT_1M_TRG_R
- osc_config2_set::ENABLE_1M_R
- osc_config2_set::MUX_1M_R
- osc_config2_set::R
- osc_config2_set::W
- osc_config2_tog::CLK_1M_ERR_FL_R
- osc_config2_tog::COUNT_1M_TRG_R
- osc_config2_tog::ENABLE_1M_R
- osc_config2_tog::MUX_1M_R
- osc_config2_tog::R
- osc_config2_tog::W