Struct imxrt1062_xtalosc24m::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _MISC0>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to oscillator.

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.

impl W<u32, Reg<u32, _MISC0_SET>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to oscillator.

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.

impl W<u32, Reg<u32, _MISC0_CLR>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to oscillator.

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.

impl W<u32, Reg<u32, _MISC0_TOG>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to oscillator.

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true.

pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W

Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.

impl W<u32, Reg<u32, _LOWPWR_CTRL>>

pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W

Bit 0 - RC Osc. enable control.

pub fn osc_sel(&mut self) -> OSC_SEL_W

Bit 4 - Select the source for the 24MHz clock.

pub fn lpbg_sel(&mut self) -> LPBG_SEL_W

Bit 5 - Bandgap select. Not related to oscillator.

pub fn lpbg_test(&mut self) -> LPBG_TEST_W

Bit 6 - Low power bandgap test bit. Not related to oscillator.

pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W

Bit 7 - Low power reftop ibias disable. Not related to oscillator.

pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W

Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.

pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W

Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.

pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W

Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.

pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W

Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.

pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W

Bit 13 - For debug purposes only

pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W

Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use

pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W

Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.

pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W

Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.

impl W<u32, Reg<u32, _LOWPWR_CTRL_SET>>

pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W

Bit 0 - RC Osc. enable control.

pub fn osc_sel(&mut self) -> OSC_SEL_W

Bit 4 - Select the source for the 24MHz clock.

pub fn lpbg_sel(&mut self) -> LPBG_SEL_W

Bit 5 - Bandgap select. Not related to oscillator.

pub fn lpbg_test(&mut self) -> LPBG_TEST_W

Bit 6 - Low power bandgap test bit. Not related to oscillator.

pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W

Bit 7 - Low power reftop ibias disable. Not related to oscillator.

pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W

Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.

pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W

Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.

pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W

Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.

pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W

Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.

pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W

Bit 13 - For debug purposes only

pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W

Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use

pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W

Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.

pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W

Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.

impl W<u32, Reg<u32, _LOWPWR_CTRL_CLR>>

pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W

Bit 0 - RC Osc. enable control.

pub fn osc_sel(&mut self) -> OSC_SEL_W

Bit 4 - Select the source for the 24MHz clock.

pub fn lpbg_sel(&mut self) -> LPBG_SEL_W

Bit 5 - Bandgap select. Not related to oscillator.

pub fn lpbg_test(&mut self) -> LPBG_TEST_W

Bit 6 - Low power bandgap test bit. Not related to oscillator.

pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W

Bit 7 - Low power reftop ibias disable. Not related to oscillator.

pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W

Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.

pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W

Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.

pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W

Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.

pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W

Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.

pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W

Bit 13 - For debug purposes only

pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W

Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use

pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W

Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.

pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W

Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.

impl W<u32, Reg<u32, _LOWPWR_CTRL_TOG>>

pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W

Bit 0 - RC Osc. enable control.

pub fn osc_sel(&mut self) -> OSC_SEL_W

Bit 4 - Select the source for the 24MHz clock.

pub fn lpbg_sel(&mut self) -> LPBG_SEL_W

Bit 5 - Bandgap select. Not related to oscillator.

pub fn lpbg_test(&mut self) -> LPBG_TEST_W

Bit 6 - Low power bandgap test bit. Not related to oscillator.

pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W

Bit 7 - Low power reftop ibias disable. Not related to oscillator.

pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W

Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.

pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W

Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.

pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W

Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.

pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W

Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.

pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W

Bit 13 - For debug purposes only

pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W

Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use

pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W

Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.

pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W

Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.

impl W<u32, Reg<u32, _OSC_CONFIG0>>

pub fn start(&mut self) -> START_W

Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.

pub fn enable(&mut self) -> ENABLE_W

Bit 1 - Enables the tuning logic to calculate new RC tuning values

pub fn bypass(&mut self) -> BYPASS_W

Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.

pub fn invert(&mut self) -> INVERT_W

Bit 3 - Invert the stepping of the calculated RC tuning value.

pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W

Bits 4:11 - RC osc. tuning values.

pub fn hyst_plus(&mut self) -> HYST_PLUS_W

Bits 12:15 - Positive hysteresis value

pub fn hyst_minus(&mut self) -> HYST_MINUS_W

Bits 16:19 - Negative hysteresis value

pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W

Bits 24:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG0_SET>>

pub fn start(&mut self) -> START_W

Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.

pub fn enable(&mut self) -> ENABLE_W

Bit 1 - Enables the tuning logic to calculate new RC tuning values

pub fn bypass(&mut self) -> BYPASS_W

Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.

pub fn invert(&mut self) -> INVERT_W

Bit 3 - Invert the stepping of the calculated RC tuning value.

pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W

Bits 4:11 - RC osc. tuning values.

pub fn hyst_plus(&mut self) -> HYST_PLUS_W

Bits 12:15 - Positive hysteresis value

pub fn hyst_minus(&mut self) -> HYST_MINUS_W

Bits 16:19 - Negative hysteresis value

pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W

Bits 24:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG0_CLR>>

pub fn start(&mut self) -> START_W

Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.

pub fn enable(&mut self) -> ENABLE_W

Bit 1 - Enables the tuning logic to calculate new RC tuning values

pub fn bypass(&mut self) -> BYPASS_W

Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.

pub fn invert(&mut self) -> INVERT_W

Bit 3 - Invert the stepping of the calculated RC tuning value.

pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W

Bits 4:11 - RC osc. tuning values.

pub fn hyst_plus(&mut self) -> HYST_PLUS_W

Bits 12:15 - Positive hysteresis value

pub fn hyst_minus(&mut self) -> HYST_MINUS_W

Bits 16:19 - Negative hysteresis value

pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W

Bits 24:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG0_TOG>>

pub fn start(&mut self) -> START_W

Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.

pub fn enable(&mut self) -> ENABLE_W

Bit 1 - Enables the tuning logic to calculate new RC tuning values

pub fn bypass(&mut self) -> BYPASS_W

Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.

pub fn invert(&mut self) -> INVERT_W

Bit 3 - Invert the stepping of the calculated RC tuning value.

pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W

Bits 4:11 - RC osc. tuning values.

pub fn hyst_plus(&mut self) -> HYST_PLUS_W

Bits 12:15 - Positive hysteresis value

pub fn hyst_minus(&mut self) -> HYST_MINUS_W

Bits 16:19 - Negative hysteresis value

pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W

Bits 24:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG1>>

pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W

Bits 0:11 - The target count used to tune the RC OSC frequency

pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W

Bits 20:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG1_SET>>

pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W

Bits 0:11 - The target count used to tune the RC OSC frequency

pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W

Bits 20:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG1_CLR>>

pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W

Bits 0:11 - The target count used to tune the RC OSC frequency

pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W

Bits 20:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG1_TOG>>

pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W

Bits 0:11 - The target count used to tune the RC OSC frequency

pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W

Bits 20:31 - The current tuning value in use.

impl W<u32, Reg<u32, _OSC_CONFIG2>>

pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W

Bits 0:11 - The target count used to tune the 1MHz clock frequency

pub fn enable_1m(&mut self) -> ENABLE_1M_W

Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.

pub fn mux_1m(&mut self) -> MUX_1M_W

Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output

pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W

Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period

impl W<u32, Reg<u32, _OSC_CONFIG2_SET>>

pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W

Bits 0:11 - The target count used to tune the 1MHz clock frequency

pub fn enable_1m(&mut self) -> ENABLE_1M_W

Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.

pub fn mux_1m(&mut self) -> MUX_1M_W

Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output

pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W

Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period

impl W<u32, Reg<u32, _OSC_CONFIG2_CLR>>

pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W

Bits 0:11 - The target count used to tune the 1MHz clock frequency

pub fn enable_1m(&mut self) -> ENABLE_1M_W

Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.

pub fn mux_1m(&mut self) -> MUX_1M_W

Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output

pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W

Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period

impl W<u32, Reg<u32, _OSC_CONFIG2_TOG>>

pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W

Bits 0:11 - The target count used to tune the 1MHz clock frequency

pub fn enable_1m(&mut self) -> ENABLE_1M_W

Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.

pub fn mux_1m(&mut self) -> MUX_1M_W

Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output

pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W

Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period