[−][src]Struct imxrt1062_xtalosc24m::W
Methods
impl<U, REG> W<U, REG>
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impl W<u32, Reg<u32, _MISC0>>
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pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W
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Bit 0 - Control bit to power-down the analog bandgap reference circuitry
pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W
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Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap
pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W
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Bits 4:6 - Not related to oscillator.
pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W
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Bit 7 - Status bit that signals the analog bandgap voltage is up and stable
pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W
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Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.
pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W
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Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
pub fn osc_i(&mut self) -> OSC_I_W
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Bits 13:14 - This field determines the bias current in the 24MHz oscillator
pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W
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Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W
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Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W
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Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W
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Bit 30 - This field powers down the 24M crystal oscillator if set true.
pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W
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Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.
impl W<u32, Reg<u32, _MISC0_SET>>
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pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W
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Bit 0 - Control bit to power-down the analog bandgap reference circuitry
pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W
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Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap
pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W
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Bits 4:6 - Not related to oscillator.
pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W
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Bit 7 - Status bit that signals the analog bandgap voltage is up and stable
pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W
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Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.
pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W
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Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
pub fn osc_i(&mut self) -> OSC_I_W
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Bits 13:14 - This field determines the bias current in the 24MHz oscillator
pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W
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Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W
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Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W
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Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W
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Bit 30 - This field powers down the 24M crystal oscillator if set true.
pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W
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Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.
impl W<u32, Reg<u32, _MISC0_CLR>>
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pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W
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Bit 0 - Control bit to power-down the analog bandgap reference circuitry
pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W
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Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap
pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W
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Bits 4:6 - Not related to oscillator.
pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W
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Bit 7 - Status bit that signals the analog bandgap voltage is up and stable
pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W
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Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.
pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W
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Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
pub fn osc_i(&mut self) -> OSC_I_W
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Bits 13:14 - This field determines the bias current in the 24MHz oscillator
pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W
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Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W
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Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W
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Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W
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Bit 30 - This field powers down the 24M crystal oscillator if set true.
pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W
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Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.
impl W<u32, Reg<u32, _MISC0_TOG>>
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pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W
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Bit 0 - Control bit to power-down the analog bandgap reference circuitry
pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W
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Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap
pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W
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Bits 4:6 - Not related to oscillator.
pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W
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Bit 7 - Status bit that signals the analog bandgap voltage is up and stable
pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W
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Bits 10:11 - Configure the analog behavior in stop mode.Not related to oscillator.
pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W
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Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.
pub fn osc_i(&mut self) -> OSC_I_W
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Bits 13:14 - This field determines the bias current in the 24MHz oscillator
pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W
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Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable.
pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W
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Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block
pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W
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Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block
pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W
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Bit 30 - This field powers down the 24M crystal oscillator if set true.
pub fn vid_pll_prediv(&mut self) -> VID_PLL_PREDIV_W
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Bit 31 - Predivider for the source clock of the PLL's. Not related to oscillator.
impl W<u32, Reg<u32, _LOWPWR_CTRL>>
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pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W
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Bit 0 - RC Osc. enable control.
pub fn osc_sel(&mut self) -> OSC_SEL_W
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Bit 4 - Select the source for the 24MHz clock.
pub fn lpbg_sel(&mut self) -> LPBG_SEL_W
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Bit 5 - Bandgap select. Not related to oscillator.
pub fn lpbg_test(&mut self) -> LPBG_TEST_W
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Bit 6 - Low power bandgap test bit. Not related to oscillator.
pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W
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Bit 7 - Low power reftop ibias disable. Not related to oscillator.
pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W
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Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.
pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W
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Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.
pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W
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Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W
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Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.
pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W
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Bit 13 - For debug purposes only
pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W
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Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W
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Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.
pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W
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Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.
impl W<u32, Reg<u32, _LOWPWR_CTRL_SET>>
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pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W
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Bit 0 - RC Osc. enable control.
pub fn osc_sel(&mut self) -> OSC_SEL_W
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Bit 4 - Select the source for the 24MHz clock.
pub fn lpbg_sel(&mut self) -> LPBG_SEL_W
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Bit 5 - Bandgap select. Not related to oscillator.
pub fn lpbg_test(&mut self) -> LPBG_TEST_W
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Bit 6 - Low power bandgap test bit. Not related to oscillator.
pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W
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Bit 7 - Low power reftop ibias disable. Not related to oscillator.
pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W
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Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.
pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W
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Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.
pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W
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Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W
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Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.
pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W
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Bit 13 - For debug purposes only
pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W
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Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W
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Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.
pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W
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Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.
impl W<u32, Reg<u32, _LOWPWR_CTRL_CLR>>
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pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W
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Bit 0 - RC Osc. enable control.
pub fn osc_sel(&mut self) -> OSC_SEL_W
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Bit 4 - Select the source for the 24MHz clock.
pub fn lpbg_sel(&mut self) -> LPBG_SEL_W
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Bit 5 - Bandgap select. Not related to oscillator.
pub fn lpbg_test(&mut self) -> LPBG_TEST_W
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Bit 6 - Low power bandgap test bit. Not related to oscillator.
pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W
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Bit 7 - Low power reftop ibias disable. Not related to oscillator.
pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W
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Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.
pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W
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Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.
pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W
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Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W
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Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.
pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W
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Bit 13 - For debug purposes only
pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W
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Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W
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Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.
pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W
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Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.
impl W<u32, Reg<u32, _LOWPWR_CTRL_TOG>>
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pub fn rc_osc_en(&mut self) -> RC_OSC_EN_W
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Bit 0 - RC Osc. enable control.
pub fn osc_sel(&mut self) -> OSC_SEL_W
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Bit 4 - Select the source for the 24MHz clock.
pub fn lpbg_sel(&mut self) -> LPBG_SEL_W
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Bit 5 - Bandgap select. Not related to oscillator.
pub fn lpbg_test(&mut self) -> LPBG_TEST_W
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Bit 6 - Low power bandgap test bit. Not related to oscillator.
pub fn reftop_ibias_off(&mut self) -> REFTOP_IBIAS_OFF_W
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Bit 7 - Low power reftop ibias disable. Not related to oscillator.
pub fn l1_pwrgate(&mut self) -> L1_PWRGATE_W
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Bit 8 - L1 power gate control. Used as software override. Not related to oscillator.
pub fn l2_pwrgate(&mut self) -> L2_PWRGATE_W
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Bit 9 - L2 power gate control. Used as software override. Not related to oscillator.
pub fn cpu_pwrgate(&mut self) -> CPU_PWRGATE_W
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Bit 10 - CPU power gate control. Used as software override. Test purpose only Not related to oscillator.
pub fn display_pwrgate(&mut self) -> DISPLAY_PWRGATE_W
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Bit 11 - Display logic power gate control. Used as software override. Not related to oscillator.
pub fn rcosc_cg_override(&mut self) -> RCOSC_CG_OVERRIDE_W
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Bit 13 - For debug purposes only
pub fn xtalosc_pwrup_delay(&mut self) -> XTALOSC_PWRUP_DELAY_W
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Bits 14:15 - Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use
pub fn mix_pwrgate(&mut self) -> MIX_PWRGATE_W
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Bit 17 - Display power gate control. Used as software mask. Set to zero to force ungated.
pub fn gpu_pwrgate(&mut self) -> GPU_PWRGATE_W
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Bit 18 - GPU power gate control. Used as software mask. Set to zero to force ungated.
impl W<u32, Reg<u32, _OSC_CONFIG0>>
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pub fn start(&mut self) -> START_W
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Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
pub fn enable(&mut self) -> ENABLE_W
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Bit 1 - Enables the tuning logic to calculate new RC tuning values
pub fn bypass(&mut self) -> BYPASS_W
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Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.
pub fn invert(&mut self) -> INVERT_W
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Bit 3 - Invert the stepping of the calculated RC tuning value.
pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W
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Bits 4:11 - RC osc. tuning values.
pub fn hyst_plus(&mut self) -> HYST_PLUS_W
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Bits 12:15 - Positive hysteresis value
pub fn hyst_minus(&mut self) -> HYST_MINUS_W
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Bits 16:19 - Negative hysteresis value
pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W
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Bits 24:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG0_SET>>
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pub fn start(&mut self) -> START_W
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Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
pub fn enable(&mut self) -> ENABLE_W
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Bit 1 - Enables the tuning logic to calculate new RC tuning values
pub fn bypass(&mut self) -> BYPASS_W
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Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.
pub fn invert(&mut self) -> INVERT_W
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Bit 3 - Invert the stepping of the calculated RC tuning value.
pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W
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Bits 4:11 - RC osc. tuning values.
pub fn hyst_plus(&mut self) -> HYST_PLUS_W
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Bits 12:15 - Positive hysteresis value
pub fn hyst_minus(&mut self) -> HYST_MINUS_W
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Bits 16:19 - Negative hysteresis value
pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W
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Bits 24:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG0_CLR>>
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pub fn start(&mut self) -> START_W
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Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
pub fn enable(&mut self) -> ENABLE_W
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Bit 1 - Enables the tuning logic to calculate new RC tuning values
pub fn bypass(&mut self) -> BYPASS_W
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Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.
pub fn invert(&mut self) -> INVERT_W
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Bit 3 - Invert the stepping of the calculated RC tuning value.
pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W
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Bits 4:11 - RC osc. tuning values.
pub fn hyst_plus(&mut self) -> HYST_PLUS_W
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Bits 12:15 - Positive hysteresis value
pub fn hyst_minus(&mut self) -> HYST_MINUS_W
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Bits 16:19 - Negative hysteresis value
pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W
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Bits 24:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG0_TOG>>
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pub fn start(&mut self) -> START_W
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Bit 0 - Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset.
pub fn enable(&mut self) -> ENABLE_W
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Bit 1 - Enables the tuning logic to calculate new RC tuning values
pub fn bypass(&mut self) -> BYPASS_W
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Bit 2 - Bypasses any calculated RC tuning value and uses the programmed register value.
pub fn invert(&mut self) -> INVERT_W
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Bit 3 - Invert the stepping of the calculated RC tuning value.
pub fn rc_osc_prog(&mut self) -> RC_OSC_PROG_W
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Bits 4:11 - RC osc. tuning values.
pub fn hyst_plus(&mut self) -> HYST_PLUS_W
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Bits 12:15 - Positive hysteresis value
pub fn hyst_minus(&mut self) -> HYST_MINUS_W
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Bits 16:19 - Negative hysteresis value
pub fn rc_osc_prog_cur(&mut self) -> RC_OSC_PROG_CUR_W
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Bits 24:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG1>>
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pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W
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Bits 0:11 - The target count used to tune the RC OSC frequency
pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W
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Bits 20:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG1_SET>>
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pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W
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Bits 0:11 - The target count used to tune the RC OSC frequency
pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W
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Bits 20:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG1_CLR>>
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pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W
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Bits 0:11 - The target count used to tune the RC OSC frequency
pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W
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Bits 20:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG1_TOG>>
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pub fn count_rc_trg(&mut self) -> COUNT_RC_TRG_W
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Bits 0:11 - The target count used to tune the RC OSC frequency
pub fn count_rc_cur(&mut self) -> COUNT_RC_CUR_W
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Bits 20:31 - The current tuning value in use.
impl W<u32, Reg<u32, _OSC_CONFIG2>>
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pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W
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Bits 0:11 - The target count used to tune the 1MHz clock frequency
pub fn enable_1m(&mut self) -> ENABLE_1M_W
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Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
pub fn mux_1m(&mut self) -> MUX_1M_W
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Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output
pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W
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Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period
impl W<u32, Reg<u32, _OSC_CONFIG2_SET>>
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pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W
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Bits 0:11 - The target count used to tune the 1MHz clock frequency
pub fn enable_1m(&mut self) -> ENABLE_1M_W
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Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
pub fn mux_1m(&mut self) -> MUX_1M_W
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Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output
pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W
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Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period
impl W<u32, Reg<u32, _OSC_CONFIG2_CLR>>
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pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W
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Bits 0:11 - The target count used to tune the 1MHz clock frequency
pub fn enable_1m(&mut self) -> ENABLE_1M_W
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Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
pub fn mux_1m(&mut self) -> MUX_1M_W
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Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output
pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W
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Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period
impl W<u32, Reg<u32, _OSC_CONFIG2_TOG>>
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pub fn count_1m_trg(&mut self) -> COUNT_1M_TRG_W
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Bits 0:11 - The target count used to tune the 1MHz clock frequency
pub fn enable_1m(&mut self) -> ENABLE_1M_W
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Bit 16 - Enable the 1MHz clock output. 0 - disabled; 1 - enabled.
pub fn mux_1m(&mut self) -> MUX_1M_W
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Bit 17 - Mux the corrected or uncorrected 1MHz clock to the output
pub fn clk_1m_err_fl(&mut self) -> CLK_1M_ERR_FL_W
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Bit 31 - Flag indicates that the count_1m count wasn't reached within 1 32kHz period
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
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T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
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T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
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T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
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impl<T, U> Into<U> for T where
U: From<T>,
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U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>,
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U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
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U: TryFrom<T>,