[−][src]Type Definition imxrt1062_usbphy1::debug_set::W
type W = W<u32, DEBUG_SET>;
Writer for register DEBUG_SET
Methods
impl W
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pub fn otgidpiolock(&mut self) -> OTGIDPIOLOCK_W
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Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
pub fn debug_interface_hold(&mut self) -> DEBUG_INTERFACE_HOLD_W
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Bit 1 - Use holding registers to assist in timing for external UTMI interface.
pub fn hstpulldown(&mut self) -> HSTPULLDOWN_W
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Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
pub fn enhstpulldown(&mut self) -> ENHSTPULLDOWN_W
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Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
pub fn tx2rxcount(&mut self) -> TX2RXCOUNT_W
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Bits 8:11 - Delay in between the end of transmit to the beginning of receive
pub fn entx2rxcount(&mut self) -> ENTX2RXCOUNT_W
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Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.
pub fn squelchresetcount(&mut self) -> SQUELCHRESETCOUNT_W
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Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.
pub fn ensquelchreset(&mut self) -> ENSQUELCHRESET_W
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Bit 24 - Set bit to allow squelch to reset high-speed receive.
pub fn squelchresetlength(&mut self) -> SQUELCHRESETLENGTH_W
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Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.
pub fn host_resume_debug(&mut self) -> HOST_RESUME_DEBUG_W
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Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
pub fn clkgate(&mut self) -> CLKGATE_W
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Bit 30 - Gate Test Clocks