[−][src]Type Definition imxrt1062_usbphy1::debug_clr::R
type R = R<u32, DEBUG_CLR>;
Reader of register DEBUG_CLR
Methods
impl R
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pub fn otgidpiolock(&self) -> OTGIDPIOLOCK_R
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Bit 0 - Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value
pub fn debug_interface_hold(&self) -> DEBUG_INTERFACE_HOLD_R
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Bit 1 - Use holding registers to assist in timing for external UTMI interface.
pub fn hstpulldown(&self) -> HSTPULLDOWN_R
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Bits 2:3 - Set bit 3 to 1 to pull down 15-KOhm on USB_DP line
pub fn enhstpulldown(&self) -> ENHSTPULLDOWN_R
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Bits 4:5 - Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown
pub fn rsvd0(&self) -> RSVD0_R
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Bits 6:7 - Reserved.
pub fn tx2rxcount(&self) -> TX2RXCOUNT_R
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Bits 8:11 - Delay in between the end of transmit to the beginning of receive
pub fn entx2rxcount(&self) -> ENTX2RXCOUNT_R
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Bit 12 - Set this bit to allow a countdown to transition in between TX and RX.
pub fn rsvd1(&self) -> RSVD1_R
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Bits 13:15 - Reserved.
pub fn squelchresetcount(&self) -> SQUELCHRESETCOUNT_R
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Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX.
pub fn rsvd2(&self) -> RSVD2_R
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Bits 21:23 - Reserved.
pub fn ensquelchreset(&self) -> ENSQUELCHRESET_R
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Bit 24 - Set bit to allow squelch to reset high-speed receive.
pub fn squelchresetlength(&self) -> SQUELCHRESETLENGTH_R
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Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles.
pub fn host_resume_debug(&self) -> HOST_RESUME_DEBUG_R
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Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1.
pub fn clkgate(&self) -> CLKGATE_R
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Bit 30 - Gate Test Clocks
pub fn rsvd3(&self) -> RSVD3_R
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Bit 31 - Reserved.