Type Definition imxrt1062_iomuxc_gpr::gpr1::W

type W = W<u32, GPR1>;

Writer for register GPR1

Methods

impl W

pub fn sai1_mclk1_sel(&mut self) -> SAI1_MCLK1_SEL_W

Bits 0:2 - SAI1 MCLK1 source select

pub fn sai1_mclk2_sel(&mut self) -> SAI1_MCLK2_SEL_W

Bits 3:5 - SAI1 MCLK2 source select

pub fn sai1_mclk3_sel(&mut self) -> SAI1_MCLK3_SEL_W

Bits 6:7 - SAI1 MCLK3 source select

pub fn sai2_mclk3_sel(&mut self) -> SAI2_MCLK3_SEL_W

Bits 8:9 - SAI2 MCLK3 source select

pub fn sai3_mclk3_sel(&mut self) -> SAI3_MCLK3_SEL_W

Bits 10:11 - SAI3 MCLK3 source select

pub fn gint(&mut self) -> GINT_W

Bit 12 - Global interrupt "0" bit (connected to ARM M7 IRQ#0 and GPC)

pub fn enet1_clk_sel(&mut self) -> ENET1_CLK_SEL_W

Bit 13 - ENET1 reference clock mode select.

pub fn enet2_clk_sel(&mut self) -> ENET2_CLK_SEL_W

Bit 14 - ENET2 reference clock mode select.

pub fn usb_exp_mode(&mut self) -> USB_EXP_MODE_W

Bit 15 - USB Exposure mode

pub fn enet1_tx_clk_dir(&mut self) -> ENET1_TX_CLK_DIR_W

Bit 17 - ENET1_TX_CLK data direction control

pub fn enet2_tx_clk_dir(&mut self) -> ENET2_TX_CLK_DIR_W

Bit 18 - ENET2_TX_CLK data direction control

pub fn sai1_mclk_dir(&mut self) -> SAI1_MCLK_DIR_W

Bit 19 - sai1.MCLK signal direction control

pub fn sai2_mclk_dir(&mut self) -> SAI2_MCLK_DIR_W

Bit 20 - sai2.MCLK signal direction control

pub fn sai3_mclk_dir(&mut self) -> SAI3_MCLK_DIR_W

Bit 21 - sai3.MCLK signal direction control

pub fn exc_mon(&mut self) -> EXC_MON_W

Bit 22 - Exclusive monitor response select of illegal command

pub fn enet_ipg_clk_s_en(&mut self) -> ENET_IPG_CLK_S_EN_W

Bit 23 - ENET and ENET2 ipg_clk_s clock gating enable

pub fn cm7_force_hclk_en(&mut self) -> CM7_FORCE_HCLK_EN_W

Bit 31 - ARM CM7 platform AHB clock enable