Struct imxrt1062_iomuxc_gpr::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _GPR1>>

pub fn sai1_mclk1_sel(&mut self) -> SAI1_MCLK1_SEL_W

Bits 0:2 - SAI1 MCLK1 source select

pub fn sai1_mclk2_sel(&mut self) -> SAI1_MCLK2_SEL_W

Bits 3:5 - SAI1 MCLK2 source select

pub fn sai1_mclk3_sel(&mut self) -> SAI1_MCLK3_SEL_W

Bits 6:7 - SAI1 MCLK3 source select

pub fn sai2_mclk3_sel(&mut self) -> SAI2_MCLK3_SEL_W

Bits 8:9 - SAI2 MCLK3 source select

pub fn sai3_mclk3_sel(&mut self) -> SAI3_MCLK3_SEL_W

Bits 10:11 - SAI3 MCLK3 source select

pub fn gint(&mut self) -> GINT_W

Bit 12 - Global interrupt "0" bit (connected to ARM M7 IRQ#0 and GPC)

pub fn enet1_clk_sel(&mut self) -> ENET1_CLK_SEL_W

Bit 13 - ENET1 reference clock mode select.

pub fn enet2_clk_sel(&mut self) -> ENET2_CLK_SEL_W

Bit 14 - ENET2 reference clock mode select.

pub fn usb_exp_mode(&mut self) -> USB_EXP_MODE_W

Bit 15 - USB Exposure mode

pub fn enet1_tx_clk_dir(&mut self) -> ENET1_TX_CLK_DIR_W

Bit 17 - ENET1_TX_CLK data direction control

pub fn enet2_tx_clk_dir(&mut self) -> ENET2_TX_CLK_DIR_W

Bit 18 - ENET2_TX_CLK data direction control

pub fn sai1_mclk_dir(&mut self) -> SAI1_MCLK_DIR_W

Bit 19 - sai1.MCLK signal direction control

pub fn sai2_mclk_dir(&mut self) -> SAI2_MCLK_DIR_W

Bit 20 - sai2.MCLK signal direction control

pub fn sai3_mclk_dir(&mut self) -> SAI3_MCLK_DIR_W

Bit 21 - sai3.MCLK signal direction control

pub fn exc_mon(&mut self) -> EXC_MON_W

Bit 22 - Exclusive monitor response select of illegal command

pub fn enet_ipg_clk_s_en(&mut self) -> ENET_IPG_CLK_S_EN_W

Bit 23 - ENET and ENET2 ipg_clk_s clock gating enable

pub fn cm7_force_hclk_en(&mut self) -> CM7_FORCE_HCLK_EN_W

Bit 31 - ARM CM7 platform AHB clock enable

impl W<u32, Reg<u32, _GPR2>>

pub fn axbs_l_ahbxl_high_priority(&mut self) -> AXBS_L_AHBXL_HIGH_PRIORITY_W

Bit 0 - AXBS_L AHBXL master has higher priority.Do not set both DMA and AHBXL to high priority.

pub fn axbs_l_dma_high_priority(&mut self) -> AXBS_L_DMA_HIGH_PRIORITY_W

Bit 1 - AXBS_L DMA master has higher priority.Do not set both DMA and AHBXL to high priority.

pub fn axbs_l_force_round_robin(&mut self) -> AXBS_L_FORCE_ROUND_ROBIN_W

Bit 2 - Force Round Robin in AXBS_L

pub fn axbs_p_m0_high_priority(&mut self) -> AXBS_P_M0_HIGH_PRIORITY_W

Bit 3 - AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority.

pub fn axbs_p_m1_high_priority(&mut self) -> AXBS_P_M1_HIGH_PRIORITY_W

Bit 4 - AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority.

pub fn axbs_p_force_round_robin(&mut self) -> AXBS_P_FORCE_ROUND_ROBIN_W

Bit 5 - Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration.

pub fn canfd_filter_bypass(&mut self) -> CANFD_FILTER_BYPASS_W

Bit 6 - Disable CANFD filter

pub fn l2_mem_en_powersaving(&mut self) -> L2_MEM_EN_POWERSAVING_W

Bit 12 - enable power saving features on L2 memory

pub fn ram_auto_clk_gating_en(&mut self) -> RAM_AUTO_CLK_GATING_EN_W

Bit 13 - Automatically gate off RAM clock when RAM is not accessed.

pub fn l2_mem_deepsleep(&mut self) -> L2_MEM_DEEPSLEEP_W

Bit 14 - control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low)

pub fn mqs_clk_div(&mut self) -> MQS_CLK_DIV_W

Bits 16:23 - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency.

pub fn mqs_sw_rst(&mut self) -> MQS_SW_RST_W

Bit 24 - MQS software reset

pub fn mqs_en(&mut self) -> MQS_EN_W

Bit 25 - MQS enable.

pub fn mqs_oversample(&mut self) -> MQS_OVERSAMPLE_W

Bit 26 - Used to control the PWM oversampling rate compared with mclk.

pub fn qtimer1_tmr_cnts_freeze(&mut self) -> QTIMER1_TMR_CNTS_FREEZE_W

Bit 28 - QTIMER1 timer counter freeze

pub fn qtimer2_tmr_cnts_freeze(&mut self) -> QTIMER2_TMR_CNTS_FREEZE_W

Bit 29 - QTIMER2 timer counter freeze

pub fn qtimer3_tmr_cnts_freeze(&mut self) -> QTIMER3_TMR_CNTS_FREEZE_W

Bit 30 - QTIMER3 timer counter freeze

pub fn qtimer4_tmr_cnts_freeze(&mut self) -> QTIMER4_TMR_CNTS_FREEZE_W

Bit 31 - QTIMER4 timer counter freeze

impl W<u32, Reg<u32, _GPR3>>

pub fn ocram_ctl(&mut self) -> OCRAM_CTL_W

Bits 0:3 - OCRAM_CTL[3]

• write address pipeline control bit

pub fn dcp_key_sel(&mut self) -> DCP_KEY_SEL_W

Bit 4 - Select 128-bit dcp key from 256-bit key from snvs/ocotp

pub fn ocram2_ctl(&mut self) -> OCRAM2_CTL_W

Bits 8:11 - OCRAM2_CTL[3]

• write address pipeline control bit

pub fn axbs_l_halt_req(&mut self) -> AXBS_L_HALT_REQ_W

Bit 15 - Request to halt axbs_l

pub fn axbs_l_halted(&mut self) -> AXBS_L_HALTED_W

Bit 31 - This bit shows the status of axbs_l

impl W<u32, Reg<u32, _GPR4>>

pub fn edma_stop_req(&mut self) -> EDMA_STOP_REQ_W

Bit 0 - EDMA stop request.

pub fn can1_stop_req(&mut self) -> CAN1_STOP_REQ_W

Bit 1 - CAN1 stop request.

pub fn can2_stop_req(&mut self) -> CAN2_STOP_REQ_W

Bit 2 - CAN2 stop request.

pub fn trng_stop_req(&mut self) -> TRNG_STOP_REQ_W

Bit 3 - TRNG stop request.

pub fn enet_stop_req(&mut self) -> ENET_STOP_REQ_W

Bit 4 - ENET stop request.

pub fn sai1_stop_req(&mut self) -> SAI1_STOP_REQ_W

Bit 5 - SAI1 stop request.

pub fn sai2_stop_req(&mut self) -> SAI2_STOP_REQ_W

Bit 6 - SAI2 stop request.

pub fn sai3_stop_req(&mut self) -> SAI3_STOP_REQ_W

Bit 7 - SAI3 stop request.

pub fn enet2_stop_req(&mut self) -> ENET2_STOP_REQ_W

Bit 8 - ENET2 stop request.

pub fn semc_stop_req(&mut self) -> SEMC_STOP_REQ_W

Bit 9 - SEMC stop request.

pub fn pit_stop_req(&mut self) -> PIT_STOP_REQ_W

Bit 10 - PIT stop request.

pub fn flexspi_stop_req(&mut self) -> FLEXSPI_STOP_REQ_W

Bit 11 - FlexSPI stop request.

pub fn flexio1_stop_req(&mut self) -> FLEXIO1_STOP_REQ_W

Bit 12 - FlexIO1 stop request.

pub fn flexio2_stop_req(&mut self) -> FLEXIO2_STOP_REQ_W

Bit 13 - FlexIO2 stop request.

pub fn flexio3_stop_req(&mut self) -> FLEXIO3_STOP_REQ_W

Bit 14 - On-platform flexio3 stop request.

pub fn flexspi2_stop_req(&mut self) -> FLEXSPI2_STOP_REQ_W

Bit 15 - FlexSPI2 stop request.

impl W<u32, Reg<u32, _GPR5>>

pub fn wdog1_mask(&mut self) -> WDOG1_MASK_W

Bit 6 - WDOG1 Timeout Mask

pub fn wdog2_mask(&mut self) -> WDOG2_MASK_W

Bit 7 - WDOG2 Timeout Mask

pub fn gpt2_capin1_sel(&mut self) -> GPT2_CAPIN1_SEL_W

Bit 23 - GPT2 input capture channel 1 source select

pub fn gpt2_capin2_sel(&mut self) -> GPT2_CAPIN2_SEL_W

Bit 24 - GPT2 input capture channel 2 source select

pub fn enet_event3in_sel(&mut self) -> ENET_EVENT3IN_SEL_W

Bit 25 - ENET input timer event3 source select

pub fn enet2_event3in_sel(&mut self) -> ENET2_EVENT3IN_SEL_W

Bit 26 - ENET2 input timer event3 source select

pub fn vref_1m_clk_gpt1(&mut self) -> VREF_1M_CLK_GPT1_W

Bit 28 - GPT1 1 MHz clock source select

pub fn vref_1m_clk_gpt2(&mut self) -> VREF_1M_CLK_GPT2_W

Bit 29 - GPT2 1 MHz clock source select

impl W<u32, Reg<u32, _GPR6>>

pub fn qtimer1_trm0_input_sel(&mut self) -> QTIMER1_TRM0_INPUT_SEL_W

Bit 0 - QTIMER1 TMR0 input select

pub fn qtimer1_trm1_input_sel(&mut self) -> QTIMER1_TRM1_INPUT_SEL_W

Bit 1 - QTIMER1 TMR1 input select

pub fn qtimer1_trm2_input_sel(&mut self) -> QTIMER1_TRM2_INPUT_SEL_W

Bit 2 - QTIMER1 TMR2 input select

pub fn qtimer1_trm3_input_sel(&mut self) -> QTIMER1_TRM3_INPUT_SEL_W

Bit 3 - QTIMER1 TMR3 input select

pub fn qtimer2_trm0_input_sel(&mut self) -> QTIMER2_TRM0_INPUT_SEL_W

Bit 4 - QTIMER2 TMR0 input select

pub fn qtimer2_trm1_input_sel(&mut self) -> QTIMER2_TRM1_INPUT_SEL_W

Bit 5 - QTIMER2 TMR1 input select

pub fn qtimer2_trm2_input_sel(&mut self) -> QTIMER2_TRM2_INPUT_SEL_W

Bit 6 - QTIMER2 TMR2 input select

pub fn qtimer2_trm3_input_sel(&mut self) -> QTIMER2_TRM3_INPUT_SEL_W

Bit 7 - QTIMER2 TMR3 input select

pub fn qtimer3_trm0_input_sel(&mut self) -> QTIMER3_TRM0_INPUT_SEL_W

Bit 8 - QTIMER3 TMR0 input select

pub fn qtimer3_trm1_input_sel(&mut self) -> QTIMER3_TRM1_INPUT_SEL_W

Bit 9 - QTIMER3 TMR1 input select

pub fn qtimer3_trm2_input_sel(&mut self) -> QTIMER3_TRM2_INPUT_SEL_W

Bit 10 - QTIMER3 TMR2 input select

pub fn qtimer3_trm3_input_sel(&mut self) -> QTIMER3_TRM3_INPUT_SEL_W

Bit 11 - QTIMER3 TMR3 input select

pub fn qtimer4_trm0_input_sel(&mut self) -> QTIMER4_TRM0_INPUT_SEL_W

Bit 12 - QTIMER4 TMR0 input select

pub fn qtimer4_trm1_input_sel(&mut self) -> QTIMER4_TRM1_INPUT_SEL_W

Bit 13 - QTIMER4 TMR1 input select

pub fn qtimer4_trm2_input_sel(&mut self) -> QTIMER4_TRM2_INPUT_SEL_W

Bit 14 - QTIMER4 TMR2 input select

pub fn qtimer4_trm3_input_sel(&mut self) -> QTIMER4_TRM3_INPUT_SEL_W

Bit 15 - QTIMER4 TMR3 input select

pub fn iomuxc_xbar_dir_sel_4(&mut self) -> IOMUXC_XBAR_DIR_SEL_4_W

Bit 16 - IOMUXC XBAR_INOUT4 function direction select

pub fn iomuxc_xbar_dir_sel_5(&mut self) -> IOMUXC_XBAR_DIR_SEL_5_W

Bit 17 - IOMUXC XBAR_INOUT5 function direction select

pub fn iomuxc_xbar_dir_sel_6(&mut self) -> IOMUXC_XBAR_DIR_SEL_6_W

Bit 18 - IOMUXC XBAR_INOUT6 function direction select

pub fn iomuxc_xbar_dir_sel_7(&mut self) -> IOMUXC_XBAR_DIR_SEL_7_W

Bit 19 - IOMUXC XBAR_INOUT7 function direction select

pub fn iomuxc_xbar_dir_sel_8(&mut self) -> IOMUXC_XBAR_DIR_SEL_8_W

Bit 20 - IOMUXC XBAR_INOUT8 function direction select

pub fn iomuxc_xbar_dir_sel_9(&mut self) -> IOMUXC_XBAR_DIR_SEL_9_W

Bit 21 - IOMUXC XBAR_INOUT9 function direction select

pub fn iomuxc_xbar_dir_sel_10(&mut self) -> IOMUXC_XBAR_DIR_SEL_10_W

Bit 22 - IOMUXC XBAR_INOUT10 function direction select

pub fn iomuxc_xbar_dir_sel_11(&mut self) -> IOMUXC_XBAR_DIR_SEL_11_W

Bit 23 - IOMUXC XBAR_INOUT11 function direction select

pub fn iomuxc_xbar_dir_sel_12(&mut self) -> IOMUXC_XBAR_DIR_SEL_12_W

Bit 24 - IOMUXC XBAR_INOUT12 function direction select

pub fn iomuxc_xbar_dir_sel_13(&mut self) -> IOMUXC_XBAR_DIR_SEL_13_W

Bit 25 - IOMUXC XBAR_INOUT13 function direction select

pub fn iomuxc_xbar_dir_sel_14(&mut self) -> IOMUXC_XBAR_DIR_SEL_14_W

Bit 26 - IOMUXC XBAR_INOUT14 function direction select

pub fn iomuxc_xbar_dir_sel_15(&mut self) -> IOMUXC_XBAR_DIR_SEL_15_W

Bit 27 - IOMUXC XBAR_INOUT15 function direction select

pub fn iomuxc_xbar_dir_sel_16(&mut self) -> IOMUXC_XBAR_DIR_SEL_16_W

Bit 28 - IOMUXC XBAR_INOUT16 function direction select

pub fn iomuxc_xbar_dir_sel_17(&mut self) -> IOMUXC_XBAR_DIR_SEL_17_W

Bit 29 - IOMUXC XBAR_INOUT17 function direction select

pub fn iomuxc_xbar_dir_sel_18(&mut self) -> IOMUXC_XBAR_DIR_SEL_18_W

Bit 30 - IOMUXC XBAR_INOUT18 function direction select

pub fn iomuxc_xbar_dir_sel_19(&mut self) -> IOMUXC_XBAR_DIR_SEL_19_W

Bit 31 - IOMUXC XBAR_INOUT19 function direction select

impl W<u32, Reg<u32, _GPR7>>

pub fn lpi2c1_stop_req(&mut self) -> LPI2C1_STOP_REQ_W

Bit 0 - LPI2C1 stop request

pub fn lpi2c2_stop_req(&mut self) -> LPI2C2_STOP_REQ_W

Bit 1 - LPI2C2 stop request

pub fn lpi2c3_stop_req(&mut self) -> LPI2C3_STOP_REQ_W

Bit 2 - LPI2C3 stop request

pub fn lpi2c4_stop_req(&mut self) -> LPI2C4_STOP_REQ_W

Bit 3 - LPI2C4 stop request

pub fn lpspi1_stop_req(&mut self) -> LPSPI1_STOP_REQ_W

Bit 4 - LPSPI1 stop request

pub fn lpspi2_stop_req(&mut self) -> LPSPI2_STOP_REQ_W

Bit 5 - LPSPI2 stop request

pub fn lpspi3_stop_req(&mut self) -> LPSPI3_STOP_REQ_W

Bit 6 - LPSPI3 stop request

pub fn lpspi4_stop_req(&mut self) -> LPSPI4_STOP_REQ_W

Bit 7 - LPSPI4 stop request

pub fn lpuart1_stop_req(&mut self) -> LPUART1_STOP_REQ_W

Bit 8 - LPUART1 stop request

pub fn lpuart2_stop_req(&mut self) -> LPUART2_STOP_REQ_W

Bit 9 - LPUART1 stop request

pub fn lpuart3_stop_req(&mut self) -> LPUART3_STOP_REQ_W

Bit 10 - LPUART3 stop request

pub fn lpuart4_stop_req(&mut self) -> LPUART4_STOP_REQ_W

Bit 11 - LPUART4 stop request

pub fn lpuart5_stop_req(&mut self) -> LPUART5_STOP_REQ_W

Bit 12 - LPUART5 stop request

pub fn lpuart6_stop_req(&mut self) -> LPUART6_STOP_REQ_W

Bit 13 - LPUART6 stop request

pub fn lpuart7_stop_req(&mut self) -> LPUART7_STOP_REQ_W

Bit 14 - LPUART7 stop request

pub fn lpuart8_stop_req(&mut self) -> LPUART8_STOP_REQ_W

Bit 15 - LPUART8 stop request

impl W<u32, Reg<u32, _GPR8>>

pub fn lpi2c1_ipg_stop_mode(&mut self) -> LPI2C1_IPG_STOP_MODE_W

Bit 0 - LPI2C1 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpi2c1_ipg_doze(&mut self) -> LPI2C1_IPG_DOZE_W

Bit 1 - LPI2C1 ipg_doze mode

pub fn lpi2c2_ipg_stop_mode(&mut self) -> LPI2C2_IPG_STOP_MODE_W

Bit 2 - LPI2C2 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpi2c2_ipg_doze(&mut self) -> LPI2C2_IPG_DOZE_W

Bit 3 - LPI2C2 ipg_doze mode

pub fn lpi2c3_ipg_stop_mode(&mut self) -> LPI2C3_IPG_STOP_MODE_W

Bit 4 - LPI2C3 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpi2c3_ipg_doze(&mut self) -> LPI2C3_IPG_DOZE_W

Bit 5 - LPI2C3 ipg_doze mode

pub fn lpi2c4_ipg_stop_mode(&mut self) -> LPI2C4_IPG_STOP_MODE_W

Bit 6 - LPI2C4 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpi2c4_ipg_doze(&mut self) -> LPI2C4_IPG_DOZE_W

Bit 7 - LPI2C4 ipg_doze mode

pub fn lpspi1_ipg_stop_mode(&mut self) -> LPSPI1_IPG_STOP_MODE_W

Bit 8 - LPSPI1 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpspi1_ipg_doze(&mut self) -> LPSPI1_IPG_DOZE_W

Bit 9 - LPSPI1 ipg_doze mode

pub fn lpspi2_ipg_stop_mode(&mut self) -> LPSPI2_IPG_STOP_MODE_W

Bit 10 - LPSPI2 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpspi2_ipg_doze(&mut self) -> LPSPI2_IPG_DOZE_W

Bit 11 - LPSPI2 ipg_doze mode

pub fn lpspi3_ipg_stop_mode(&mut self) -> LPSPI3_IPG_STOP_MODE_W

Bit 12 - LPSPI3 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpspi3_ipg_doze(&mut self) -> LPSPI3_IPG_DOZE_W

Bit 13 - LPSPI3 ipg_doze mode

pub fn lpspi4_ipg_stop_mode(&mut self) -> LPSPI4_IPG_STOP_MODE_W

Bit 14 - LPSPI4 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpspi4_ipg_doze(&mut self) -> LPSPI4_IPG_DOZE_W

Bit 15 - LPSPI4 ipg_doze mode

pub fn lpuart1_ipg_stop_mode(&mut self) -> LPUART1_IPG_STOP_MODE_W

Bit 16 - LPUART1 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart1_ipg_doze(&mut self) -> LPUART1_IPG_DOZE_W

Bit 17 - LPUART1 ipg_doze mode

pub fn lpuart2_ipg_stop_mode(&mut self) -> LPUART2_IPG_STOP_MODE_W

Bit 18 - LPUART2 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart2_ipg_doze(&mut self) -> LPUART2_IPG_DOZE_W

Bit 19 - LPUART2 ipg_doze mode

pub fn lpuart3_ipg_stop_mode(&mut self) -> LPUART3_IPG_STOP_MODE_W

Bit 20 - LPUART3 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart3_ipg_doze(&mut self) -> LPUART3_IPG_DOZE_W

Bit 21 - LPUART3 ipg_doze mode

pub fn lpuart4_ipg_stop_mode(&mut self) -> LPUART4_IPG_STOP_MODE_W

Bit 22 - LPUART4 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart4_ipg_doze(&mut self) -> LPUART4_IPG_DOZE_W

Bit 23 - LPUART4 ipg_doze mode

pub fn lpuart5_ipg_stop_mode(&mut self) -> LPUART5_IPG_STOP_MODE_W

Bit 24 - LPUART5 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart5_ipg_doze(&mut self) -> LPUART5_IPG_DOZE_W

Bit 25 - LPUART5 ipg_doze mode

pub fn lpuart6_ipg_stop_mode(&mut self) -> LPUART6_IPG_STOP_MODE_W

Bit 26 - LPUART6 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart6_ipg_doze(&mut self) -> LPUART6_IPG_DOZE_W

Bit 27 - LPUART6 ipg_doze mode

pub fn lpuart7_ipg_stop_mode(&mut self) -> LPUART7_IPG_STOP_MODE_W

Bit 28 - LPUART7 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart7_ipg_doze(&mut self) -> LPUART7_IPG_DOZE_W

Bit 29 - LPUART7 ipg_doze mode

pub fn lpuart8_ipg_stop_mode(&mut self) -> LPUART8_IPG_STOP_MODE_W

Bit 30 - LPUART8 stop mode selection, cannot change when ipg_stop is asserted.

pub fn lpuart8_ipg_doze(&mut self) -> LPUART8_IPG_DOZE_W

Bit 31 - LPUART8 ipg_doze mode

impl W<u32, Reg<u32, _GPR10>>

pub fn niden(&mut self) -> NIDEN_W

Bit 0 - ARM non-secure (non-invasive) debug enable

pub fn dbg_en(&mut self) -> DBG_EN_W

Bit 1 - ARM invasive debug enable

pub fn sec_err_resp(&mut self) -> SEC_ERR_RESP_W

Bit 2 - Security error response enable for all security gaskets (on both AHB and AXI buses)

pub fn dcpkey_ocotp_or_keymux(&mut self) -> DCPKEY_OCOTP_OR_KEYMUX_W

Bit 4 - DCP Key selection bit.

pub fn ocram_tz_en(&mut self) -> OCRAM_TZ_EN_W

Bit 8 - OCRAM TrustZone (TZ) enable.

pub fn ocram_tz_addr(&mut self) -> OCRAM_TZ_ADDR_W

Bits 9:15 - OCRAM TrustZone (TZ) start address

pub fn lock_niden(&mut self) -> LOCK_NIDEN_W

Bit 16 - Lock NIDEN field for changes

pub fn lock_dbg_en(&mut self) -> LOCK_DBG_EN_W

Bit 17 - Lock DBG_EN field for changes

pub fn lock_sec_err_resp(&mut self) -> LOCK_SEC_ERR_RESP_W

Bit 18 - Lock SEC_ERR_RESP field for changes

pub fn lock_dcpkey_ocotp_or_keymux(&mut self) -> LOCK_DCPKEY_OCOTP_OR_KEYMUX_W

Bit 20 - Lock DCP Key OCOTP/Key MUX selection bit

pub fn lock_ocram_tz_en(&mut self) -> LOCK_OCRAM_TZ_EN_W

Bit 24 - Lock OCRAM_TZ_EN field for changes

pub fn lock_ocram_tz_addr(&mut self) -> LOCK_OCRAM_TZ_ADDR_W

Bits 25:31 - Lock OCRAM_TZ_ADDR field for changes

impl W<u32, Reg<u32, _GPR11>>

pub fn m7_apc_ac_r0_ctrl(&mut self) -> M7_APC_AC_R0_CTRL_W

Bits 0:1 - Access control of memory region-0

pub fn m7_apc_ac_r1_ctrl(&mut self) -> M7_APC_AC_R1_CTRL_W

Bits 2:3 - Access control of memory region-1

pub fn m7_apc_ac_r2_ctrl(&mut self) -> M7_APC_AC_R2_CTRL_W

Bits 4:5 - Access control of memory region-2

pub fn m7_apc_ac_r3_ctrl(&mut self) -> M7_APC_AC_R3_CTRL_W

Bits 6:7 - Access control of memory region-3

pub fn bee_de_rx_en(&mut self) -> BEE_DE_RX_EN_W

Bits 8:11 - BEE data decryption of memory region-n (n = 3 to 0)

impl W<u32, Reg<u32, _GPR12>>

pub fn flexio1_ipg_stop_mode(&mut self) -> FLEXIO1_IPG_STOP_MODE_W

Bit 0 - FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted.

pub fn flexio1_ipg_doze(&mut self) -> FLEXIO1_IPG_DOZE_W

Bit 1 - FLEXIO1 ipg_doze mode

pub fn flexio2_ipg_stop_mode(&mut self) -> FLEXIO2_IPG_STOP_MODE_W

Bit 2 - FlexIO2 stop mode selection. Cannot change when ipg_stop is asserted.

pub fn flexio2_ipg_doze(&mut self) -> FLEXIO2_IPG_DOZE_W

Bit 3 - FLEXIO2 ipg_doze mode

pub fn acmp_ipg_stop_mode(&mut self) -> ACMP_IPG_STOP_MODE_W

Bit 4 - ACMP stop mode selection. Cannot change when ipg_stop is asserted.

pub fn flexio3_ipg_stop_mode(&mut self) -> FLEXIO3_IPG_STOP_MODE_W

Bit 5 - FlexIO3 stop mode selection. Cannot change when ipg_stop is asserted.

pub fn flexio3_ipg_doze(&mut self) -> FLEXIO3_IPG_DOZE_W

Bit 6 - FLEXIO3 ipg_doze mode

impl W<u32, Reg<u32, _GPR13>>

pub fn arcache_usdhc(&mut self) -> ARCACHE_USDHC_W

Bit 0 - uSDHC block cacheable attribute value of AXI read transactions

pub fn awcache_usdhc(&mut self) -> AWCACHE_USDHC_W

Bit 1 - uSDHC block cacheable attribute value of AXI write transactions

pub fn canfd_stop_req(&mut self) -> CANFD_STOP_REQ_W

Bit 4 - CANFD stop request.

pub fn cache_enet(&mut self) -> CACHE_ENET_W

Bit 7 - ENET block cacheable attribute value of AXI transactions

pub fn cache_usb(&mut self) -> CACHE_USB_W

Bit 13 - USB block cacheable attribute value of AXI transactions

impl W<u32, Reg<u32, _GPR14>>

pub fn acmp1_cmp_igen_trim_dn(&mut self) -> ACMP1_CMP_IGEN_TRIM_DN_W

Bit 0 - reduces ACMP1 internal bias current by 30%

pub fn acmp2_cmp_igen_trim_dn(&mut self) -> ACMP2_CMP_IGEN_TRIM_DN_W

Bit 1 - reduces ACMP2 internal bias current by 30%

pub fn acmp3_cmp_igen_trim_dn(&mut self) -> ACMP3_CMP_IGEN_TRIM_DN_W

Bit 2 - reduces ACMP3 internal bias current by 30%

pub fn acmp4_cmp_igen_trim_dn(&mut self) -> ACMP4_CMP_IGEN_TRIM_DN_W

Bit 3 - reduces ACMP4 internal bias current by 30%

pub fn acmp1_cmp_igen_trim_up(&mut self) -> ACMP1_CMP_IGEN_TRIM_UP_W

Bit 4 - increases ACMP1 internal bias current by 30%

pub fn acmp2_cmp_igen_trim_up(&mut self) -> ACMP2_CMP_IGEN_TRIM_UP_W

Bit 5 - increases ACMP2 internal bias current by 30%

pub fn acmp3_cmp_igen_trim_up(&mut self) -> ACMP3_CMP_IGEN_TRIM_UP_W

Bit 6 - increases ACMP3 internal bias current by 30%

pub fn acmp4_cmp_igen_trim_up(&mut self) -> ACMP4_CMP_IGEN_TRIM_UP_W

Bit 7 - increases ACMP4 internal bias current by 30%

pub fn acmp1_sample_sync_en(&mut self) -> ACMP1_SAMPLE_SYNC_EN_W

Bit 8 - ACMP1 sample_lv source select

pub fn acmp2_sample_sync_en(&mut self) -> ACMP2_SAMPLE_SYNC_EN_W

Bit 9 - ACMP2 sample_lv source select

pub fn acmp3_sample_sync_en(&mut self) -> ACMP3_SAMPLE_SYNC_EN_W

Bit 10 - ACMP3 sample_lv source select

pub fn acmp4_sample_sync_en(&mut self) -> ACMP4_SAMPLE_SYNC_EN_W

Bit 11 - ACMP4 sample_lv source select

pub fn cm7_cfgitcmsz(&mut self) -> CM7_CFGITCMSZ_W

Bits 16:19 - ITCM total size configuration

pub fn cm7_cfgdtcmsz(&mut self) -> CM7_CFGDTCMSZ_W

Bits 20:23 - DTCM total size configuration

impl W<u32, Reg<u32, _GPR16>>

pub fn init_itcm_en(&mut self) -> INIT_ITCM_EN_W

Bit 0 - ITCM enable initialization out of reset

pub fn init_dtcm_en(&mut self) -> INIT_DTCM_EN_W

Bit 1 - DTCM enable initialization out of reset

pub fn flexram_bank_cfg_sel(&mut self) -> FLEXRAM_BANK_CFG_SEL_W

Bit 2 - FlexRAM bank config source select

impl W<u32, Reg<u32, _GPR17>>

pub fn flexram_bank_cfg(&mut self) -> FLEXRAM_BANK_CFG_W

Bits 0:31 - FlexRAM bank config value

impl W<u32, Reg<u32, _GPR18>>

pub fn lock_m7_apc_ac_r0_bot(&mut self) -> LOCK_M7_APC_AC_R0_BOT_W

Bit 0 - lock M7_APC_AC_R0_BOT field for changes

pub fn m7_apc_ac_r0_bot(&mut self) -> M7_APC_AC_R0_BOT_W

Bits 3:31 - APC end address of memory region-0

impl W<u32, Reg<u32, _GPR19>>

pub fn lock_m7_apc_ac_r0_top(&mut self) -> LOCK_M7_APC_AC_R0_TOP_W

Bit 0 - lock M7_APC_AC_R0_TOP field for changes

pub fn m7_apc_ac_r0_top(&mut self) -> M7_APC_AC_R0_TOP_W

Bits 3:31 - APC start address of memory region-0

impl W<u32, Reg<u32, _GPR20>>

pub fn lock_m7_apc_ac_r1_bot(&mut self) -> LOCK_M7_APC_AC_R1_BOT_W

Bit 0 - lock M7_APC_AC_R1_BOT field for changes

pub fn m7_apc_ac_r1_bot(&mut self) -> M7_APC_AC_R1_BOT_W

Bits 3:31 - APC end address of memory region-1

impl W<u32, Reg<u32, _GPR21>>

pub fn lock_m7_apc_ac_r1_top(&mut self) -> LOCK_M7_APC_AC_R1_TOP_W

Bit 0 - lock M7_APC_AC_R1_TOP field for changes

pub fn m7_apc_ac_r1_top(&mut self) -> M7_APC_AC_R1_TOP_W

Bits 3:31 - APC start address of memory region-1

impl W<u32, Reg<u32, _GPR22>>

pub fn lock_m7_apc_ac_r2_bot(&mut self) -> LOCK_M7_APC_AC_R2_BOT_W

Bit 0 - lock M7_APC_AC_R2_BOT field for changes

pub fn m7_apc_ac_r2_bot(&mut self) -> M7_APC_AC_R2_BOT_W

Bits 3:31 - APC end address of memory region-2

impl W<u32, Reg<u32, _GPR23>>

pub fn lock_m7_apc_ac_r2_top(&mut self) -> LOCK_M7_APC_AC_R2_TOP_W

Bit 0 - lock M7_APC_AC_R2_TOP field for changes

pub fn m7_apc_ac_r2_top(&mut self) -> M7_APC_AC_R2_TOP_W

Bits 3:31 - APC start address of memory region-2

impl W<u32, Reg<u32, _GPR24>>

pub fn lock_m7_apc_ac_r3_bot(&mut self) -> LOCK_M7_APC_AC_R3_BOT_W

Bit 0 - lock M7_APC_AC_R3_BOT field for changes

pub fn m7_apc_ac_r3_bot(&mut self) -> M7_APC_AC_R3_BOT_W

Bits 3:31 - APC end address of memory region-3

impl W<u32, Reg<u32, _GPR25>>

pub fn lock_m7_apc_ac_r3_top(&mut self) -> LOCK_M7_APC_AC_R3_TOP_W

Bit 0 - lock M7_APC_AC_R3_TOP field for changes

pub fn m7_apc_ac_r3_top(&mut self) -> M7_APC_AC_R3_TOP_W

Bits 3:31 - APC start address of memory region-3

impl W<u32, Reg<u32, _GPR26>>

pub fn gpio_mux1_gpio_sel(&mut self) -> GPIO_MUX1_GPIO_SEL_W

Bits 0:31 - GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function.

impl W<u32, Reg<u32, _GPR27>>

pub fn gpio_mux2_gpio_sel(&mut self) -> GPIO_MUX2_GPIO_SEL_W

Bits 0:31 - GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function.

impl W<u32, Reg<u32, _GPR28>>

pub fn gpio_mux3_gpio_sel(&mut self) -> GPIO_MUX3_GPIO_SEL_W

Bits 0:31 - GPIO3 and GPIO8 share same IO MUX function, GPIO_MUX3 selects one GPIO function.

impl W<u32, Reg<u32, _GPR29>>

pub fn gpio_mux4_gpio_sel(&mut self) -> GPIO_MUX4_GPIO_SEL_W

Bits 0:31 - GPIO4 and GPIO9 share same IO MUX function, GPIO_MUX4 selects one GPIO function.

impl W<u32, Reg<u32, _GPR30>>

pub fn flexspi_remap_addr_start(&mut self) -> FLEXSPI_REMAP_ADDR_START_W

Bits 12:31 - Start address of flexspi1 and flexspi2

impl W<u32, Reg<u32, _GPR31>>

pub fn flexspi_remap_addr_end(&mut self) -> FLEXSPI_REMAP_ADDR_END_W

Bits 12:31 - End address of flexspi1 and flexspi2

impl W<u32, Reg<u32, _GPR32>>

pub fn flexspi_remap_addr_offset(&mut self) -> FLEXSPI_REMAP_ADDR_OFFSET_W

Bits 12:31 - Offset address of flexspi1 and flexspi2

impl W<u32, Reg<u32, _GPR33>>

pub fn ocram2_tz_en(&mut self) -> OCRAM2_TZ_EN_W

Bit 0 - OCRAM2 TrustZone (TZ) enable.

pub fn ocram2_tz_addr(&mut self) -> OCRAM2_TZ_ADDR_W

Bits 1:7 - OCRAM2 TrustZone (TZ) start address

pub fn lock_ocram2_tz_en(&mut self) -> LOCK_OCRAM2_TZ_EN_W

Bit 16 - Lock OCRAM2_TZ_EN field for changes

pub fn lock_ocram2_tz_addr(&mut self) -> LOCK_OCRAM2_TZ_ADDR_W

Bits 17:23 - Lock OCRAM2_TZ_ADDR field for changes

impl W<u32, Reg<u32, _GPR34>>

pub fn sip_test_mux_boot_pin_sel(&mut self) -> SIP_TEST_MUX_BOOT_PIN_SEL_W

Bits 0:7 - Boot Pin select in SIP_TEST_MUX

pub fn sip_test_mux_qspi_sip_en(&mut self) -> SIP_TEST_MUX_QSPI_SIP_EN_W

Bit 8 - Enable SIP_TEST_MUX