Type Definition imxrt1062_ccm::cs1cdr::W

type W = W<u32, CS1CDR>;

Writer for register CS1CDR

Methods

impl W

pub fn sai1_clk_podf(&mut self) -> SAI1_CLK_PODF_W

Bits 0:5 - Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

pub fn sai1_clk_pred(&mut self) -> SAI1_CLK_PRED_W

Bits 6:8 - Divider for sai1 clock pred.

pub fn flexio2_clk_pred(&mut self) -> FLEXIO2_CLK_PRED_W

Bits 9:11 - Divider for flexio2/flexio3 clock.

pub fn sai3_clk_podf(&mut self) -> SAI3_CLK_PODF_W

Bits 16:21 - Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

pub fn sai3_clk_pred(&mut self) -> SAI3_CLK_PRED_W

Bits 22:24 - Divider for sai3/adc1/adc2 clock pred.

pub fn flexio2_clk_podf(&mut self) -> FLEXIO2_CLK_PODF_W

Bits 25:27 - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated.