Struct imxrt1062_ccm::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CCR>>

pub fn oscnt(&mut self) -> OSCNT_W

Bits 0:7 - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened.

pub fn cosc_en(&mut self) -> COSC_EN_W

Bit 12 - On chip oscillator enable bit - this bit value is reflected on the output cosc_en

pub fn reg_bypass_count(&mut self) -> REG_BYPASS_COUNT_W

Bits 21:26 - Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ

pub fn rbc_en(&mut self) -> RBC_EN_W

Bit 27 - Enable for REG_BYPASS_COUNTER

impl W<u32, Reg<u32, _CCSR>>

pub fn pll3_sw_clk_sel(&mut self) -> PLL3_SW_CLK_SEL_W

Bit 0 - Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes.

impl W<u32, Reg<u32, _CACRR>>

pub fn arm_podf(&mut self) -> ARM_PODF_W

Bits 0:2 - Divider for ARM clock root

impl W<u32, Reg<u32, _CBCDR>>

pub fn semc_clk_sel(&mut self) -> SEMC_CLK_SEL_W

Bit 6 - SEMC clock source select

pub fn semc_alt_clk_sel(&mut self) -> SEMC_ALT_CLK_SEL_W

Bit 7 - SEMC alternative clock select

pub fn ipg_podf(&mut self) -> IPG_PODF_W

Bits 8:9 - Divider for ipg podf.

pub fn ahb_podf(&mut self) -> AHB_PODF_W

Bits 10:12 - Divider for AHB PODF

pub fn semc_podf(&mut self) -> SEMC_PODF_W

Bits 16:18 - Post divider for SEMC clock

pub fn periph_clk_sel(&mut self) -> PERIPH_CLK_SEL_W

Bit 25 - Selector for peripheral main clock

pub fn periph_clk2_podf(&mut self) -> PERIPH_CLK2_PODF_W

Bits 27:29 - Divider for periph_clk2_podf.

impl W<u32, Reg<u32, _CBCMR>>

pub fn lpspi_clk_sel(&mut self) -> LPSPI_CLK_SEL_W

Bits 4:5 - Selector for lpspi clock multiplexer

pub fn flexspi2_clk_sel(&mut self) -> FLEXSPI2_CLK_SEL_W

Bits 8:9 - Selector for flexspi2 clock multiplexer

pub fn periph_clk2_sel(&mut self) -> PERIPH_CLK2_SEL_W

Bits 12:13 - Selector for peripheral clk2 clock multiplexer

pub fn trace_clk_sel(&mut self) -> TRACE_CLK_SEL_W

Bits 14:15 - Selector for Trace clock multiplexer

pub fn pre_periph_clk_sel(&mut self) -> PRE_PERIPH_CLK_SEL_W

Bits 18:19 - Selector for pre_periph clock multiplexer

pub fn lcdif_podf(&mut self) -> LCDIF_PODF_W

Bits 23:25 - Post-divider for LCDIF clock.

pub fn lpspi_podf(&mut self) -> LPSPI_PODF_W

Bits 26:28 - Divider for LPSPI. Divider should be updated when output clock is gated.

pub fn flexspi2_podf(&mut self) -> FLEXSPI2_PODF_W

Bits 29:31 - Divider for flexspi2 clock root.

impl W<u32, Reg<u32, _CSCMR1>>

pub fn perclk_podf(&mut self) -> PERCLK_PODF_W

Bits 0:5 - Divider for perclk podf.

pub fn perclk_clk_sel(&mut self) -> PERCLK_CLK_SEL_W

Bit 6 - Selector for the perclk clock multiplexor

pub fn sai1_clk_sel(&mut self) -> SAI1_CLK_SEL_W

Bits 10:11 - Selector for sai1 clock multiplexer

pub fn sai2_clk_sel(&mut self) -> SAI2_CLK_SEL_W

Bits 12:13 - Selector for sai2 clock multiplexer

pub fn sai3_clk_sel(&mut self) -> SAI3_CLK_SEL_W

Bits 14:15 - Selector for sai3/adc1/adc2 clock multiplexer

pub fn usdhc1_clk_sel(&mut self) -> USDHC1_CLK_SEL_W

Bit 16 - Selector for usdhc1 clock multiplexer

pub fn usdhc2_clk_sel(&mut self) -> USDHC2_CLK_SEL_W

Bit 17 - Selector for usdhc2 clock multiplexer

pub fn flexspi_podf(&mut self) -> FLEXSPI_PODF_W

Bits 23:25 - Divider for flexspi clock root.

pub fn flexspi_clk_sel(&mut self) -> FLEXSPI_CLK_SEL_W

Bits 29:30 - Selector for flexspi clock multiplexer

impl W<u32, Reg<u32, _CSCMR2>>

pub fn can_clk_podf(&mut self) -> CAN_CLK_PODF_W

Bits 2:7 - Divider for CAN/CANFD clock podf.

pub fn can_clk_sel(&mut self) -> CAN_CLK_SEL_W

Bits 8:9 - Selector for CAN/CANFD clock multiplexer

pub fn flexio2_clk_sel(&mut self) -> FLEXIO2_CLK_SEL_W

Bits 19:20 - Selector for flexio2/flexio3 clock multiplexer

impl W<u32, Reg<u32, _CSCDR1>>

pub fn uart_clk_podf(&mut self) -> UART_CLK_PODF_W

Bits 0:5 - Divider for uart clock podf.

pub fn uart_clk_sel(&mut self) -> UART_CLK_SEL_W

Bit 6 - Selector for the UART clock multiplexor

pub fn usdhc1_podf(&mut self) -> USDHC1_PODF_W

Bits 11:13 - Divider for usdhc1 clock podf. Divider should be updated when output clock is gated.

pub fn usdhc2_podf(&mut self) -> USDHC2_PODF_W

Bits 16:18 - Divider for usdhc2 clock. Divider should be updated when output clock is gated.

pub fn trace_podf(&mut self) -> TRACE_PODF_W

Bits 25:26 - Divider for trace clock. Divider should be updated when output clock is gated.

impl W<u32, Reg<u32, _CS1CDR>>

pub fn sai1_clk_podf(&mut self) -> SAI1_CLK_PODF_W

Bits 0:5 - Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

pub fn sai1_clk_pred(&mut self) -> SAI1_CLK_PRED_W

Bits 6:8 - Divider for sai1 clock pred.

pub fn flexio2_clk_pred(&mut self) -> FLEXIO2_CLK_PRED_W

Bits 9:11 - Divider for flexio2/flexio3 clock.

pub fn sai3_clk_podf(&mut self) -> SAI3_CLK_PODF_W

Bits 16:21 - Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

pub fn sai3_clk_pred(&mut self) -> SAI3_CLK_PRED_W

Bits 22:24 - Divider for sai3/adc1/adc2 clock pred.

pub fn flexio2_clk_podf(&mut self) -> FLEXIO2_CLK_PODF_W

Bits 25:27 - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated.

impl W<u32, Reg<u32, _CS2CDR>>

pub fn sai2_clk_podf(&mut self) -> SAI2_CLK_PODF_W

Bits 0:5 - Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

pub fn sai2_clk_pred(&mut self) -> SAI2_CLK_PRED_W

Bits 6:8 - Divider for sai2 clock pred.Divider should be updated when output clock is gated.

impl W<u32, Reg<u32, _CDCDR>>

pub fn flexio1_clk_sel(&mut self) -> FLEXIO1_CLK_SEL_W

Bits 7:8 - Selector for flexio1 clock multiplexer

pub fn flexio1_clk_podf(&mut self) -> FLEXIO1_CLK_PODF_W

Bits 9:11 - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.

pub fn flexio1_clk_pred(&mut self) -> FLEXIO1_CLK_PRED_W

Bits 12:14 - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.

pub fn spdif0_clk_sel(&mut self) -> SPDIF0_CLK_SEL_W

Bits 20:21 - Selector for spdif0 clock multiplexer

pub fn spdif0_clk_podf(&mut self) -> SPDIF0_CLK_PODF_W

Bits 22:24 - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.

pub fn spdif0_clk_pred(&mut self) -> SPDIF0_CLK_PRED_W

Bits 25:27 - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.

impl W<u32, Reg<u32, _CSCDR2>>

pub fn lcdif_pred(&mut self) -> LCDIF_PRED_W

Bits 12:14 - Pre-divider for lcdif clock. Divider should be updated when output clock is gated.

pub fn lcdif_pre_clk_sel(&mut self) -> LCDIF_PRE_CLK_SEL_W

Bits 15:17 - Selector for lcdif root clock pre-multiplexer

pub fn lpi2c_clk_sel(&mut self) -> LPI2C_CLK_SEL_W

Bit 18 - Selector for the LPI2C clock multiplexor

pub fn lpi2c_clk_podf(&mut self) -> LPI2C_CLK_PODF_W

Bits 19:24 - Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.

impl W<u32, Reg<u32, _CSCDR3>>

pub fn csi_clk_sel(&mut self) -> CSI_CLK_SEL_W

Bits 9:10 - Selector for csi_mclk multiplexer

pub fn csi_podf(&mut self) -> CSI_PODF_W

Bits 11:13 - Post divider for csi_mclk. Divider should be updated when output clock is gated.

impl W<u32, Reg<u32, _CLPCR>>

pub fn lpm(&mut self) -> LPM_W

Bits 0:1 - Setting the low power mode that system will enter on next assertion of dsm_request signal.

pub fn arm_clk_dis_on_lpm(&mut self) -> ARM_CLK_DIS_ON_LPM_W

Bit 5 - Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode

pub fn sbyos(&mut self) -> SBYOS_W

Bit 6 - Standby clock oscillator bit

pub fn dis_ref_osc(&mut self) -> DIS_REF_OSC_W

Bit 7 - dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i

pub fn vstby(&mut self) -> VSTBY_W

Bit 8 - Voltage standby request bit

pub fn stby_count(&mut self) -> STBY_COUNT_W

Bits 9:10 - Standby counter definition

pub fn cosc_pwrdown(&mut self) -> COSC_PWRDOWN_W

Bit 11 - In run mode, software can manually control powering down of on chip oscillator, i

pub fn bypass_lpm_hs1(&mut self) -> BYPASS_LPM_HS1_W

Bit 19 - Bypass low power mode handshake. This bit should always be set to 1'b1 by software.

pub fn bypass_lpm_hs0(&mut self) -> BYPASS_LPM_HS0_W

Bit 21 - Bypass low power mode handshake. This bit should always be set to 1'b1 by software.

pub fn mask_core0_wfi(&mut self) -> MASK_CORE0_WFI_W

Bit 22 - Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request

pub fn mask_scu_idle(&mut self) -> MASK_SCU_IDLE_W

Bit 26 - Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request

pub fn mask_l2cc_idle(&mut self) -> MASK_L2CC_IDLE_W

Bit 27 - Mask L2CC IDLE for entering low power mode

impl W<u32, Reg<u32, _CISR>>

pub fn lrf_pll(&mut self) -> LRF_PLL_W

Bit 0 - CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs

pub fn cosc_ready(&mut self) -> COSC_READY_W

Bit 6 - CCM interrupt request 2 generated due to on board oscillator ready, i

pub fn semc_podf_loaded(&mut self) -> SEMC_PODF_LOADED_W

Bit 17 - CCM interrupt request 1 generated due to frequency change of semc_podf

pub fn periph2_clk_sel_loaded(&mut self) -> PERIPH2_CLK_SEL_LOADED_W

Bit 19 - CCM interrupt request 1 generated due to frequency change of periph2_clk_sel

pub fn ahb_podf_loaded(&mut self) -> AHB_PODF_LOADED_W

Bit 20 - CCM interrupt request 1 generated due to frequency change of ahb_podf

pub fn periph_clk_sel_loaded(&mut self) -> PERIPH_CLK_SEL_LOADED_W

Bit 22 - CCM interrupt request 1 generated due to update of periph_clk_sel.

pub fn arm_podf_loaded(&mut self) -> ARM_PODF_LOADED_W

Bit 26 - CCM interrupt request 1 generated due to frequency change of arm_podf

impl W<u32, Reg<u32, _CIMR>>

pub fn mask_lrf_pll(&mut self) -> MASK_LRF_PLL_W

Bit 0 - mask interrupt generation due to lrf of PLLs

pub fn mask_cosc_ready(&mut self) -> MASK_COSC_READY_W

Bit 6 - mask interrupt generation due to on board oscillator ready

pub fn mask_semc_podf_loaded(&mut self) -> MASK_SEMC_PODF_LOADED_W

Bit 17 - mask interrupt generation due to frequency change of semc_podf

pub fn mask_periph2_clk_sel_loaded(&mut self) -> MASK_PERIPH2_CLK_SEL_LOADED_W

Bit 19 - mask interrupt generation due to update of periph2_clk_sel.

pub fn mask_ahb_podf_loaded(&mut self) -> MASK_AHB_PODF_LOADED_W

Bit 20 - mask interrupt generation due to frequency change of ahb_podf

pub fn mask_periph_clk_sel_loaded(&mut self) -> MASK_PERIPH_CLK_SEL_LOADED_W

Bit 22 - mask interrupt generation due to update of periph_clk_sel.

pub fn arm_podf_loaded(&mut self) -> ARM_PODF_LOADED_W

Bit 26 - mask interrupt generation due to frequency change of arm_podf

impl W<u32, Reg<u32, _CCOSR>>

pub fn clko1_sel(&mut self) -> CLKO1_SEL_W

Bits 0:3 - Selection of the clock to be generated on CCM_CLKO1

pub fn clko1_div(&mut self) -> CLKO1_DIV_W

Bits 4:6 - Setting the divider of CCM_CLKO1

pub fn clko1_en(&mut self) -> CLKO1_EN_W

Bit 7 - Enable of CCM_CLKO1 clock

pub fn clk_out_sel(&mut self) -> CLK_OUT_SEL_W

Bit 8 - CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks

pub fn clko2_sel(&mut self) -> CLKO2_SEL_W

Bits 16:20 - Selection of the clock to be generated on CCM_CLKO2

pub fn clko2_div(&mut self) -> CLKO2_DIV_W

Bits 21:23 - Setting the divider of CCM_CLKO2

pub fn clko2_en(&mut self) -> CLKO2_EN_W

Bit 24 - Enable of CCM_CLKO2 clock

impl W<u32, Reg<u32, _CGPR>>

pub fn pmic_delay_scaler(&mut self) -> PMIC_DELAY_SCALER_W

Bit 0 - Defines clock dividion of clock for stby_count (pmic delay counter)

pub fn efuse_prog_supply_gate(&mut self) -> EFUSE_PROG_SUPPLY_GATE_W

Bit 4 - Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing

pub fn sys_mem_ds_ctrl(&mut self) -> SYS_MEM_DS_CTRL_W

Bits 14:15 - System memory DS control

pub fn fpl(&mut self) -> FPL_W

Bit 16 - Fast PLL enable.

pub fn int_mem_clk_lpm(&mut self) -> INT_MEM_CLK_LPM_W

Bit 17 - Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal

impl W<u32, Reg<u32, _CCGR0>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - aips_tz1 clocks (aips_tz1_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - aips_tz2 clocks (aips_tz2_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - mqs clock ( mqs_hmclk_clock_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - flexspi_exsc clock (flexspi_exsc_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - sim_m or sim_main register access clock (sim_m_mainclk_r_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - dcp clock (dcp_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - lpuart3 clock (lpuart3_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - can1 clock (can1_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - can1_serial clock (can1_serial_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - can2 clock (can2_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - can2_serial clock (can2_serial_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - trace clock (trace_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - gpt2 bus clocks (gpt2_bus_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - gpt2 serial clocks (gpt2_serial_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - lpuart2 clock (lpuart2_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - gpio2_clocks (gpio2_clk_enable)

impl W<u32, Reg<u32, _CCGR1>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - lpspi1 clocks (lpspi1_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - lpspi2 clocks (lpspi2_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - lpspi3 clocks (lpspi3_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - lpspi4 clocks (lpspi4_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - adc2 clock (adc2_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - enet clock (enet_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - pit clocks (pit_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - aoi2 clocks (aoi2_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - adc1 clock (adc1_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - semc_exsc clock (semc_exsc_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - gpt1 bus clock (gpt_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - gpt1 serial clock (gpt_serial_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - lpuart4 clock (lpuart4_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - gpio1 clock (gpio1_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - csu clock (csu_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - Reserved

impl W<u32, Reg<u32, _CCGR2>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - ocram_exsc clock (ocram_exsc_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - csi clock (csi_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - iomuxc_snvs clock (iomuxc_snvs_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - lpi2c1 clock (lpi2c1_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - lpi2c2 clock (lpi2c2_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - lpi2c3 clock (lpi2c3_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - OCOTP_CTRL clock (iim_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - xbar3 clock (xbar3_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - ipmux1 clock (ipmux1_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - ipmux2 clock (ipmux2_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - ipmux3 clock (ipmux3_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - xbar1 clock (xbar1_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - xbar2 clock (xbar2_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - gpio3 clock (gpio3_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - lcd clocks (lcd_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - pxp clocks (pxp_clk_enable)

impl W<u32, Reg<u32, _CCGR3>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - flexio2 clocks (flexio2_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - lpuart5 clock (lpuart5_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - semc clocks (semc_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - lpuart6 clock (lpuart6_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - aoi1 clock (aoi1_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - lcdif pix clock (lcdif_pix_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - gpio4 clock (gpio4_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - ewm clocks (ewm_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - wdog1 clock (wdog1_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - flexram clock (flexram_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - acmp1 clocks (acmp1_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - acmp2 clocks (acmp2_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - acmp3 clocks (acmp3_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - acmp4 clocks (acmp4_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - The OCRAM clock cannot be turned off when the CM cache is running on this device.

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable)

impl W<u32, Reg<u32, _CCGR4>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - sim_m7 register access clock (sim_m7_mainclk_r_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - iomuxc clock (iomuxc_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - iomuxc gpr clock (iomuxc_gpr_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - bee clock(bee_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - sim_m7 clock (sim_m7_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - tsc_dig clock (tsc_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - sim_m clocks (sim_m_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - sim_ems clocks (sim_ems_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - pwm1 clocks (pwm1_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - pwm2 clocks (pwm2_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - pwm3 clocks (pwm3_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - pwm4 clocks (pwm4_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - enc1 clocks (enc1_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - enc2 clocks (enc2_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - enc3 clocks (enc3_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - enc4 clocks (enc4_clk_enable)

impl W<u32, Reg<u32, _CCGR5>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - rom clock (rom_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - flexio1 clock (flexio1_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - wdog3 clock (wdog3_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - dma clock (dma_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - kpp clock (kpp_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - wdog2 clock (wdog2_clk_enable)

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - aipstz4 clocks (aips_tz4_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - spdif clock (spdif_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - sim_main clock (sim_main_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - sai1 clock (sai1_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - sai2 clock (sai2_clk_enable)

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - sai3 clock (sai3_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - lpuart1 clock (lpuart1_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - lpuart7 clock (lpuart7_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - snvs_hp clock (snvs_hp_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - snvs_lp clock (snvs_lp_clk_enable)

impl W<u32, Reg<u32, _CCGR6>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - usboh3 clock (usboh3_clk_enable)

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - usdhc1 clocks (usdhc1_clk_enable)

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - usdhc2 clocks (usdhc2_clk_enable)

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - dcdc clocks (dcdc_clk_enable)

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - ipmux4 clock (ipmux4_clk_enable)

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - trng clock (trng_clk_enable)

pub fn cg7(&mut self) -> CG7_W

Bits 14:15 - lpuart8 clocks (lpuart8_clk_enable)

pub fn cg8(&mut self) -> CG8_W

Bits 16:17 - timer4 clocks (timer4_clk_enable)

pub fn cg9(&mut self) -> CG9_W

Bits 18:19 - aips_tz3 clock (aips_tz3_clk_enable)

pub fn cg10(&mut self) -> CG10_W

Bits 20:21 - sim_axbs_p_clk_enable

pub fn cg11(&mut self) -> CG11_W

Bits 22:23 - anadig clocks (anadig_clk_enable)

pub fn cg12(&mut self) -> CG12_W

Bits 24:25 - lpi2c4 serial clock (lpi2c4_serial_clk_enable)

pub fn cg13(&mut self) -> CG13_W

Bits 26:27 - timer1 clocks (timer1_clk_enable)

pub fn cg14(&mut self) -> CG14_W

Bits 28:29 - timer2 clocks (timer2_clk_enable)

pub fn cg15(&mut self) -> CG15_W

Bits 30:31 - timer3 clocks (timer3_clk_enable)

impl W<u32, Reg<u32, _CCGR7>>

pub fn cg0(&mut self) -> CG0_W

Bits 0:1 - enet2_clk_enable

pub fn cg1(&mut self) -> CG1_W

Bits 2:3 - flexspi2_clk_enable

pub fn cg2(&mut self) -> CG2_W

Bits 4:5 - axbs_l_clk_enable

pub fn cg3(&mut self) -> CG3_W

Bits 6:7 - can3_clk_enable

pub fn cg4(&mut self) -> CG4_W

Bits 8:9 - can3_serial_clk_enable

pub fn cg5(&mut self) -> CG5_W

Bits 10:11 - aips_lite_clk_enable

pub fn cg6(&mut self) -> CG6_W

Bits 12:13 - flexio3_clk_enable

impl W<u32, Reg<u32, _CMEOR>>

pub fn mod_en_ov_gpt(&mut self) -> MOD_EN_OV_GPT_W

Bit 5 - Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk'

pub fn mod_en_ov_pit(&mut self) -> MOD_EN_OV_PIT_W

Bit 6 - Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk'

pub fn mod_en_usdhc(&mut self) -> MOD_EN_USDHC_W

Bit 7 - overide clock enable signal from USDHC.

pub fn mod_en_ov_trng(&mut self) -> MOD_EN_OV_TRNG_W

Bit 9 - Overide clock enable signal from TRNG

pub fn mod_en_ov_canfd_cpi(&mut self) -> MOD_EN_OV_CANFD_CPI_W

Bit 10 - Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN's signal 'enable_clk_cpi'

pub fn mod_en_ov_can2_cpi(&mut self) -> MOD_EN_OV_CAN2_CPI_W

Bit 28 - Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi'

pub fn mod_en_ov_can1_cpi(&mut self) -> MOD_EN_OV_CAN1_CPI_W

Bit 30 - Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi'