[−][src]Type Definition imxrt1062_ccm::ccgr5::W
type W = W<u32, CCGR5>;
Writer for register CCGR5
Methods
impl W
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pub fn cg0(&mut self) -> CG0_W
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Bits 0:1 - rom clock (rom_clk_enable)
pub fn cg1(&mut self) -> CG1_W
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Bits 2:3 - flexio1 clock (flexio1_clk_enable)
pub fn cg2(&mut self) -> CG2_W
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Bits 4:5 - wdog3 clock (wdog3_clk_enable)
pub fn cg3(&mut self) -> CG3_W
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Bits 6:7 - dma clock (dma_clk_enable)
pub fn cg4(&mut self) -> CG4_W
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Bits 8:9 - kpp clock (kpp_clk_enable)
pub fn cg5(&mut self) -> CG5_W
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Bits 10:11 - wdog2 clock (wdog2_clk_enable)
pub fn cg6(&mut self) -> CG6_W
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Bits 12:13 - aipstz4 clocks (aips_tz4_clk_enable)
pub fn cg7(&mut self) -> CG7_W
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Bits 14:15 - spdif clock (spdif_clk_enable)
pub fn cg8(&mut self) -> CG8_W
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Bits 16:17 - sim_main clock (sim_main_clk_enable)
pub fn cg9(&mut self) -> CG9_W
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Bits 18:19 - sai1 clock (sai1_clk_enable)
pub fn cg10(&mut self) -> CG10_W
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Bits 20:21 - sai2 clock (sai2_clk_enable)
pub fn cg11(&mut self) -> CG11_W
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Bits 22:23 - sai3 clock (sai3_clk_enable)
pub fn cg12(&mut self) -> CG12_W
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Bits 24:25 - lpuart1 clock (lpuart1_clk_enable)
pub fn cg13(&mut self) -> CG13_W
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Bits 26:27 - lpuart7 clock (lpuart7_clk_enable)
pub fn cg14(&mut self) -> CG14_W
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Bits 28:29 - snvs_hp clock (snvs_hp_clk_enable)
pub fn cg15(&mut self) -> CG15_W
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Bits 30:31 - snvs_lp clock (snvs_lp_clk_enable)