[−][src]Struct imxrt1062_ccm_analog::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub pll_arm: PLL_ARM,
    pub pll_arm_set: PLL_ARM_SET,
    pub pll_arm_clr: PLL_ARM_CLR,
    pub pll_arm_tog: PLL_ARM_TOG,
    pub pll_usb1: PLL_USB1,
    pub pll_usb1_set: PLL_USB1_SET,
    pub pll_usb1_clr: PLL_USB1_CLR,
    pub pll_usb1_tog: PLL_USB1_TOG,
    pub pll_usb2: PLL_USB2,
    pub pll_usb2_set: PLL_USB2_SET,
    pub pll_usb2_clr: PLL_USB2_CLR,
    pub pll_usb2_tog: PLL_USB2_TOG,
    pub pll_sys: PLL_SYS,
    pub pll_sys_set: PLL_SYS_SET,
    pub pll_sys_clr: PLL_SYS_CLR,
    pub pll_sys_tog: PLL_SYS_TOG,
    pub pll_sys_ss: PLL_SYS_SS,
    pub pll_sys_num: PLL_SYS_NUM,
    pub pll_sys_denom: PLL_SYS_DENOM,
    pub pll_audio: PLL_AUDIO,
    pub pll_audio_set: PLL_AUDIO_SET,
    pub pll_audio_clr: PLL_AUDIO_CLR,
    pub pll_audio_tog: PLL_AUDIO_TOG,
    pub pll_audio_num: PLL_AUDIO_NUM,
    pub pll_audio_denom: PLL_AUDIO_DENOM,
    pub pll_video: PLL_VIDEO,
    pub pll_video_set: PLL_VIDEO_SET,
    pub pll_video_clr: PLL_VIDEO_CLR,
    pub pll_video_tog: PLL_VIDEO_TOG,
    pub pll_video_num: PLL_VIDEO_NUM,
    pub pll_video_denom: PLL_VIDEO_DENOM,
    pub pll_enet: PLL_ENET,
    pub pll_enet_set: PLL_ENET_SET,
    pub pll_enet_clr: PLL_ENET_CLR,
    pub pll_enet_tog: PLL_ENET_TOG,
    pub pfd_480: PFD_480,
    pub pfd_480_set: PFD_480_SET,
    pub pfd_480_clr: PFD_480_CLR,
    pub pfd_480_tog: PFD_480_TOG,
    pub pfd_528: PFD_528,
    pub pfd_528_set: PFD_528_SET,
    pub pfd_528_clr: PFD_528_CLR,
    pub pfd_528_tog: PFD_528_TOG,
    pub misc0: MISC0,
    pub misc0_set: MISC0_SET,
    pub misc0_clr: MISC0_CLR,
    pub misc0_tog: MISC0_TOG,
    pub misc1: MISC1,
    pub misc1_set: MISC1_SET,
    pub misc1_clr: MISC1_CLR,
    pub misc1_tog: MISC1_TOG,
    pub misc2: MISC2,
    pub misc2_set: MISC2_SET,
    pub misc2_clr: MISC2_CLR,
    pub misc2_tog: MISC2_TOG,
    // some fields omitted
}

Register block

Fields

pll_arm: PLL_ARM

0x00 - Analog ARM PLL control Register

pll_arm_set: PLL_ARM_SET

0x04 - Analog ARM PLL control Register

pll_arm_clr: PLL_ARM_CLR

0x08 - Analog ARM PLL control Register

pll_arm_tog: PLL_ARM_TOG

0x0c - Analog ARM PLL control Register

pll_usb1: PLL_USB1

0x10 - Analog USB1 480MHz PLL Control Register

pll_usb1_set: PLL_USB1_SET

0x14 - Analog USB1 480MHz PLL Control Register

pll_usb1_clr: PLL_USB1_CLR

0x18 - Analog USB1 480MHz PLL Control Register

pll_usb1_tog: PLL_USB1_TOG

0x1c - Analog USB1 480MHz PLL Control Register

pll_usb2: PLL_USB2

0x20 - Analog USB2 480MHz PLL Control Register

pll_usb2_set: PLL_USB2_SET

0x24 - Analog USB2 480MHz PLL Control Register

pll_usb2_clr: PLL_USB2_CLR

0x28 - Analog USB2 480MHz PLL Control Register

pll_usb2_tog: PLL_USB2_TOG

0x2c - Analog USB2 480MHz PLL Control Register

pll_sys: PLL_SYS

0x30 - Analog System PLL Control Register

pll_sys_set: PLL_SYS_SET

0x34 - Analog System PLL Control Register

pll_sys_clr: PLL_SYS_CLR

0x38 - Analog System PLL Control Register

pll_sys_tog: PLL_SYS_TOG

0x3c - Analog System PLL Control Register

pll_sys_ss: PLL_SYS_SS

0x40 - 528MHz System PLL Spread Spectrum Register

pll_sys_num: PLL_SYS_NUM

0x50 - Numerator of 528MHz System PLL Fractional Loop Divider Register

pll_sys_denom: PLL_SYS_DENOM

0x60 - Denominator of 528MHz System PLL Fractional Loop Divider Register

pll_audio: PLL_AUDIO

0x70 - Analog Audio PLL control Register

pll_audio_set: PLL_AUDIO_SET

0x74 - Analog Audio PLL control Register

pll_audio_clr: PLL_AUDIO_CLR

0x78 - Analog Audio PLL control Register

pll_audio_tog: PLL_AUDIO_TOG

0x7c - Analog Audio PLL control Register

pll_audio_num: PLL_AUDIO_NUM

0x80 - Numerator of Audio PLL Fractional Loop Divider Register

pll_audio_denom: PLL_AUDIO_DENOM

0x90 - Denominator of Audio PLL Fractional Loop Divider Register

pll_video: PLL_VIDEO

0xa0 - Analog Video PLL control Register

pll_video_set: PLL_VIDEO_SET

0xa4 - Analog Video PLL control Register

pll_video_clr: PLL_VIDEO_CLR

0xa8 - Analog Video PLL control Register

pll_video_tog: PLL_VIDEO_TOG

0xac - Analog Video PLL control Register

pll_video_num: PLL_VIDEO_NUM

0xb0 - Numerator of Video PLL Fractional Loop Divider Register

pll_video_denom: PLL_VIDEO_DENOM

0xc0 - Denominator of Video PLL Fractional Loop Divider Register

pll_enet: PLL_ENET

0xe0 - Analog ENET PLL Control Register

pll_enet_set: PLL_ENET_SET

0xe4 - Analog ENET PLL Control Register

pll_enet_clr: PLL_ENET_CLR

0xe8 - Analog ENET PLL Control Register

pll_enet_tog: PLL_ENET_TOG

0xec - Analog ENET PLL Control Register

pfd_480: PFD_480

0xf0 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

pfd_480_set: PFD_480_SET

0xf4 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

pfd_480_clr: PFD_480_CLR

0xf8 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

pfd_480_tog: PFD_480_TOG

0xfc - 480MHz Clock (PLL3) Phase Fractional Divider Control Register

pfd_528: PFD_528

0x100 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

pfd_528_set: PFD_528_SET

0x104 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

pfd_528_clr: PFD_528_CLR

0x108 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

pfd_528_tog: PFD_528_TOG

0x10c - 528MHz Clock (PLL2) Phase Fractional Divider Control Register

misc0: MISC0

0x150 - Miscellaneous Register 0

misc0_set: MISC0_SET

0x154 - Miscellaneous Register 0

misc0_clr: MISC0_CLR

0x158 - Miscellaneous Register 0

misc0_tog: MISC0_TOG

0x15c - Miscellaneous Register 0

misc1: MISC1

0x160 - Miscellaneous Register 1

misc1_set: MISC1_SET

0x164 - Miscellaneous Register 1

misc1_clr: MISC1_CLR

0x168 - Miscellaneous Register 1

misc1_tog: MISC1_TOG

0x16c - Miscellaneous Register 1

misc2: MISC2

0x170 - Miscellaneous Register 2

misc2_set: MISC2_SET

0x174 - Miscellaneous Register 2

misc2_clr: MISC2_CLR

0x178 - Miscellaneous Register 2

misc2_tog: MISC2_TOG

0x17c - Miscellaneous Register 2

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