[][src]Type Definition imxrt1062_ccm_analog::PFD_480_CLR

type PFD_480_CLR = Reg<u32, _PFD_480_CLR>;

480MHz Clock (PLL3) Phase Fractional Divider Control Register

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see pfd_480_clr module

Trait Implementations

impl Readable for PFD_480_CLR[src]

read() method returns pfd_480_clr::R reader structure

impl ResetValue for PFD_480_CLR[src]

Register PFD_480_CLR reset()'s with value 0x1311_100c

type Type = u32

Register size

impl Writable for PFD_480_CLR[src]

write(|w| ..) method takes pfd_480_clr::W writer structure