Type Definition imxrt1062_ccm_analog::misc2_clr::R

type R = R<u32, MISC2_CLR>;

Reader of register MISC2_CLR

Methods

impl R

pub fn reg0_bo_offset(&self) -> REG0_BO_OFFSET_R

Bits 0:2 - This field defines the brown out voltage offset for the CORE power domain

pub fn reg0_bo_status(&self) -> REG0_BO_STATUS_R

Bit 3 - Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_enable_bo(&self) -> REG0_ENABLE_BO_R

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_ok(&self) -> REG0_OK_R

Bit 6 - ARM supply Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&self) -> PLL3_DISABLE_R

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_bo_offset(&self) -> REG1_BO_OFFSET_R

Bits 8:10 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg1_bo_status(&self) -> REG1_BO_STATUS_R

Bit 11 - Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_enable_bo(&self) -> REG1_ENABLE_BO_R

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_ok(&self) -> REG1_OK_R

Bit 14 - GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&self) -> AUDIO_DIV_LSB_R

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_bo_offset(&self) -> REG2_BO_OFFSET_R

Bits 16:18 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg2_bo_status(&self) -> REG2_BO_STATUS_R

Bit 19 - Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_enable_bo(&self) -> REG2_ENABLE_BO_R

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_ok(&self) -> REG2_OK_R

Bit 22 - Signals that the voltage is above the brownout level for the SOC supply

pub fn audio_div_msb(&self) -> AUDIO_DIV_MSB_R

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&self) -> REG0_STEP_TIME_R

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&self) -> REG1_STEP_TIME_R

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&self) -> REG2_STEP_TIME_R

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&self) -> VIDEO_DIV_R

Bits 30:31 - Post-divider for video