Struct imxrt1062_ccm_analog::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy, 

pub fn bits(&self) -> U

Read raw bits from register/field

impl<FI> R<bool, FI>

pub fn bit(&self) -> bool

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool

Returns true if the bit is set (1)

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ARM>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn pll_sel(&self) -> PLL_SEL_R

Bit 19 - Reserved

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ARM_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn pll_sel(&self) -> PLL_SEL_R

Bit 19 - Reserved

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ARM_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn pll_sel(&self) -> PLL_SEL_R

Bit 19 - Reserved

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ARM_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn pll_sel(&self) -> PLL_SEL_R

Bit 19 - Reserved

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<bool, EN_USB_CLKS_A>

pub fn variant(&self) -> EN_USB_CLKS_A

Get enumerated values variant

pub fn is_en_usb_clks_0(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_0

pub fn is_en_usb_clks_1(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_1

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB1>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<bool, EN_USB_CLKS_A>

pub fn variant(&self) -> EN_USB_CLKS_A

Get enumerated values variant

pub fn is_en_usb_clks_0(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_0

pub fn is_en_usb_clks_1(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_1

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB1_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<bool, EN_USB_CLKS_A>

pub fn variant(&self) -> EN_USB_CLKS_A

Get enumerated values variant

pub fn is_en_usb_clks_0(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_0

pub fn is_en_usb_clks_1(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_1

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB1_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<bool, EN_USB_CLKS_A>

pub fn variant(&self) -> EN_USB_CLKS_A

Get enumerated values variant

pub fn is_en_usb_clks_0(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_0

pub fn is_en_usb_clks_1(&self) -> bool

Checks if the value of the field is EN_USB_CLKS_1

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB1_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB2>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB2_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB2_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_USB2_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&self) -> EN_USB_CLKS_R

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&self) -> POWER_R

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_SYS>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_SYS_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_SYS_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_SYS_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<bool, ENABLE_A>

pub fn variant(&self) -> ENABLE_A

Get enumerated values variant

pub fn is_enable_0(&self) -> bool

Checks if the value of the field is ENABLE_0

pub fn is_enable_1(&self) -> bool

Checks if the value of the field is ENABLE_1

impl R<u32, Reg<u32, _PLL_SYS_SS>>

pub fn step(&self) -> STEP_R

Bits 0:14 - Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.

pub fn enable(&self) -> ENABLE_R

Bit 15 - Enable bit

pub fn stop(&self) -> STOP_R

Bits 16:31 - Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.

impl R<u32, Reg<u32, _PLL_SYS_NUM>>

pub fn a(&self) -> A_R

Bits 0:29 - 30 bit numerator (A) of fractional loop divider (signed integer).

impl R<u32, Reg<u32, _PLL_SYS_DENOM>>

pub fn b(&self) -> B_R

Bits 0:29 - 30 bit Denominator (B) of fractional loop divider (unsigned integer).

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_AUDIO>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_AUDIO_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_AUDIO_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_AUDIO_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked. 0 - PLL is not currently locked.

impl R<u32, Reg<u32, _PLL_AUDIO_NUM>>

pub fn a(&self) -> A_R

Bits 0:29 - 30 bit numerator of fractional loop divider.

impl R<u32, Reg<u32, _PLL_AUDIO_DENOM>>

pub fn b(&self) -> B_R

Bits 0:29 - 30 bit Denominator of fractional loop divider.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_VIDEO>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_VIDEO_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_VIDEO_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u8, POST_DIV_SELECT_A>

pub fn variant(&self) -> Variant<u8, POST_DIV_SELECT_A>

Get enumerated values variant

pub fn is_post_div_select_0(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_0

pub fn is_post_div_select_1(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_1

pub fn is_post_div_select_2(&self) -> bool

Checks if the value of the field is POST_DIV_SELECT_2

impl R<u32, Reg<u32, _PLL_VIDEO_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn post_div_select(&self) -> POST_DIV_SELECT_R

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u32, Reg<u32, _PLL_VIDEO_NUM>>

pub fn a(&self) -> A_R

Bits 0:29 - 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator

impl R<u32, Reg<u32, _PLL_VIDEO_DENOM>>

pub fn b(&self) -> B_R

Bits 0:29 - 30 bit Denominator of fractional loop divider.

impl R<u8, ENET2_DIV_SELECT_A>

pub fn variant(&self) -> ENET2_DIV_SELECT_A

Get enumerated values variant

pub fn is_enet2_div_select_0(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_0

pub fn is_enet2_div_select_1(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_1

pub fn is_enet2_div_select_2(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_2

pub fn is_enet2_div_select_3(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_3

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ENET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&self) -> ENET2_DIV_SELECT_R

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&self) -> ENET2_REF_EN_R

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&self) -> ENET_25M_REF_EN_R

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, ENET2_DIV_SELECT_A>

pub fn variant(&self) -> ENET2_DIV_SELECT_A

Get enumerated values variant

pub fn is_enet2_div_select_0(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_0

pub fn is_enet2_div_select_1(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_1

pub fn is_enet2_div_select_2(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_2

pub fn is_enet2_div_select_3(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_3

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ENET_SET>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&self) -> ENET2_DIV_SELECT_R

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&self) -> ENET2_REF_EN_R

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&self) -> ENET_25M_REF_EN_R

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, ENET2_DIV_SELECT_A>

pub fn variant(&self) -> ENET2_DIV_SELECT_A

Get enumerated values variant

pub fn is_enet2_div_select_0(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_0

pub fn is_enet2_div_select_1(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_1

pub fn is_enet2_div_select_2(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_2

pub fn is_enet2_div_select_3(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_3

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ENET_CLR>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&self) -> ENET2_DIV_SELECT_R

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&self) -> ENET2_REF_EN_R

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&self) -> ENET_25M_REF_EN_R

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u8, ENET2_DIV_SELECT_A>

pub fn variant(&self) -> ENET2_DIV_SELECT_A

Get enumerated values variant

pub fn is_enet2_div_select_0(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_0

pub fn is_enet2_div_select_1(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_1

pub fn is_enet2_div_select_2(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_2

pub fn is_enet2_div_select_3(&self) -> bool

Checks if the value of the field is ENET2_DIV_SELECT_3

impl R<u8, BYPASS_CLK_SRC_A>

pub fn variant(&self) -> Variant<u8, BYPASS_CLK_SRC_A>

Get enumerated values variant

pub fn is_ref_clk_24m(&self) -> bool

Checks if the value of the field is REF_CLK_24M

pub fn is_clk1(&self) -> bool

Checks if the value of the field is CLK1

impl R<u32, Reg<u32, _PLL_ENET_TOG>>

pub fn div_select(&self) -> DIV_SELECT_R

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&self) -> ENET2_DIV_SELECT_R

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&self) -> POWERDOWN_R

Bit 12 - Powers down the PLL.

pub fn enable(&self) -> ENABLE_R

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R

Bits 14:15 - Determines the bypass source.

pub fn bypass(&self) -> BYPASS_R

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&self) -> ENET2_REF_EN_R

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&self) -> ENET_25M_REF_EN_R

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

pub fn lock(&self) -> LOCK_R

Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked.

impl R<u32, Reg<u32, _PFD_480>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_480_SET>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_480_CLR>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_480_TOG>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_528>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_528_SET>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_528_CLR>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<u32, Reg<u32, _PFD_528_TOG>>

pub fn pfd0_frac(&self) -> PFD0_FRAC_R

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_stable(&self) -> PFD0_STABLE_R

Bit 6 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd0_clkgate(&self) -> PFD0_CLKGATE_R

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&self) -> PFD1_FRAC_R

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_stable(&self) -> PFD1_STABLE_R

Bit 14 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd1_clkgate(&self) -> PFD1_CLKGATE_R

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&self) -> PFD2_FRAC_R

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_stable(&self) -> PFD2_STABLE_R

Bit 22 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd2_clkgate(&self) -> PFD2_CLKGATE_R

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&self) -> PFD3_FRAC_R

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_stable(&self) -> PFD3_STABLE_R

Bit 30 - This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code

pub fn pfd3_clkgate(&self) -> PFD3_CLKGATE_R

Bit 31 - IO Clock Gate

impl R<bool, REFTOP_SELFBIASOFF_A>

pub fn variant(&self) -> REFTOP_SELFBIASOFF_A

Get enumerated values variant

pub fn is_reftop_selfbiasoff_0(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_0

pub fn is_reftop_selfbiasoff_1(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_1

impl R<u8, REFTOP_VBGADJ_A>

pub fn variant(&self) -> REFTOP_VBGADJ_A

Get enumerated values variant

pub fn is_reftop_vbgadj_0(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_0

pub fn is_reftop_vbgadj_1(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_1

pub fn is_reftop_vbgadj_2(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_2

pub fn is_reftop_vbgadj_3(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_3

pub fn is_reftop_vbgadj_4(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_4

pub fn is_reftop_vbgadj_5(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_5

pub fn is_reftop_vbgadj_6(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_6

pub fn is_reftop_vbgadj_7(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_7

impl R<u8, STOP_MODE_CONFIG_A>

pub fn variant(&self) -> STOP_MODE_CONFIG_A

Get enumerated values variant

pub fn is_stop_mode_config_0(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_0

pub fn is_stop_mode_config_1(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_1

pub fn is_stop_mode_config_2(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_2

pub fn is_stop_mode_config_3(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_3

impl R<bool, DISCON_HIGH_SNVS_A>

pub fn variant(&self) -> DISCON_HIGH_SNVS_A

Get enumerated values variant

pub fn is_discon_high_snvs_0(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_0

pub fn is_discon_high_snvs_1(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_1

impl R<u8, OSC_I_A>

pub fn variant(&self) -> OSC_I_A

Get enumerated values variant

pub fn is_nominal(&self) -> bool

Checks if the value of the field is NOMINAL

pub fn is_minus_12_5_percent(&self) -> bool

Checks if the value of the field is MINUS_12_5_PERCENT

pub fn is_minus_25_percent(&self) -> bool

Checks if the value of the field is MINUS_25_PERCENT

pub fn is_minus_37_5_percent(&self) -> bool

Checks if the value of the field is MINUS_37_5_PERCENT

impl R<bool, CLKGATE_CTRL_A>

pub fn variant(&self) -> CLKGATE_CTRL_A

Get enumerated values variant

pub fn is_allow_auto_gate(&self) -> bool

Checks if the value of the field is ALLOW_AUTO_GATE

pub fn is_no_auto_gate(&self) -> bool

Checks if the value of the field is NO_AUTO_GATE

impl R<u8, CLKGATE_DELAY_A>

pub fn variant(&self) -> CLKGATE_DELAY_A

Get enumerated values variant

pub fn is_clkgate_delay_0(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_0

pub fn is_clkgate_delay_1(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_1

pub fn is_clkgate_delay_2(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_2

pub fn is_clkgate_delay_3(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_3

pub fn is_clkgate_delay_4(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_4

pub fn is_clkgate_delay_5(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_5

pub fn is_clkgate_delay_6(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_6

pub fn is_clkgate_delay_7(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_7

impl R<bool, RTC_XTAL_SOURCE_A>

pub fn variant(&self) -> RTC_XTAL_SOURCE_A

Get enumerated values variant

pub fn is_rtc_xtal_source_0(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_0

pub fn is_rtc_xtal_source_1(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_1

impl R<u32, Reg<u32, _MISC0>>

pub fn reftop_pwd(&self) -> REFTOP_PWD_R

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&self) -> REFTOP_SELFBIASOFF_R

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&self) -> REFTOP_VBGADJ_R

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&self) -> REFTOP_VBGUP_R

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&self) -> STOP_MODE_CONFIG_R

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&self) -> DISCON_HIGH_SNVS_R

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&self) -> OSC_I_R

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok(&self) -> OSC_XTALOK_R

Bit 15 - Status bit that signals that the output of the 24-MHz crystal oscillator is stable

pub fn osc_xtalok_en(&self) -> OSC_XTALOK_EN_R

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&self) -> CLKGATE_CTRL_R

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&self) -> CLKGATE_DELAY_R

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&self) -> RTC_XTAL_SOURCE_R

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&self) -> XTAL_24M_PWD_R

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl R<bool, REFTOP_SELFBIASOFF_A>

pub fn variant(&self) -> REFTOP_SELFBIASOFF_A

Get enumerated values variant

pub fn is_reftop_selfbiasoff_0(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_0

pub fn is_reftop_selfbiasoff_1(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_1

impl R<u8, REFTOP_VBGADJ_A>

pub fn variant(&self) -> REFTOP_VBGADJ_A

Get enumerated values variant

pub fn is_reftop_vbgadj_0(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_0

pub fn is_reftop_vbgadj_1(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_1

pub fn is_reftop_vbgadj_2(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_2

pub fn is_reftop_vbgadj_3(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_3

pub fn is_reftop_vbgadj_4(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_4

pub fn is_reftop_vbgadj_5(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_5

pub fn is_reftop_vbgadj_6(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_6

pub fn is_reftop_vbgadj_7(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_7

impl R<u8, STOP_MODE_CONFIG_A>

pub fn variant(&self) -> STOP_MODE_CONFIG_A

Get enumerated values variant

pub fn is_stop_mode_config_0(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_0

pub fn is_stop_mode_config_1(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_1

pub fn is_stop_mode_config_2(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_2

pub fn is_stop_mode_config_3(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_3

impl R<bool, DISCON_HIGH_SNVS_A>

pub fn variant(&self) -> DISCON_HIGH_SNVS_A

Get enumerated values variant

pub fn is_discon_high_snvs_0(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_0

pub fn is_discon_high_snvs_1(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_1

impl R<u8, OSC_I_A>

pub fn variant(&self) -> OSC_I_A

Get enumerated values variant

pub fn is_nominal(&self) -> bool

Checks if the value of the field is NOMINAL

pub fn is_minus_12_5_percent(&self) -> bool

Checks if the value of the field is MINUS_12_5_PERCENT

pub fn is_minus_25_percent(&self) -> bool

Checks if the value of the field is MINUS_25_PERCENT

pub fn is_minus_37_5_percent(&self) -> bool

Checks if the value of the field is MINUS_37_5_PERCENT

impl R<bool, CLKGATE_CTRL_A>

pub fn variant(&self) -> CLKGATE_CTRL_A

Get enumerated values variant

pub fn is_allow_auto_gate(&self) -> bool

Checks if the value of the field is ALLOW_AUTO_GATE

pub fn is_no_auto_gate(&self) -> bool

Checks if the value of the field is NO_AUTO_GATE

impl R<u8, CLKGATE_DELAY_A>

pub fn variant(&self) -> CLKGATE_DELAY_A

Get enumerated values variant

pub fn is_clkgate_delay_0(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_0

pub fn is_clkgate_delay_1(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_1

pub fn is_clkgate_delay_2(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_2

pub fn is_clkgate_delay_3(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_3

pub fn is_clkgate_delay_4(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_4

pub fn is_clkgate_delay_5(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_5

pub fn is_clkgate_delay_6(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_6

pub fn is_clkgate_delay_7(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_7

impl R<bool, RTC_XTAL_SOURCE_A>

pub fn variant(&self) -> RTC_XTAL_SOURCE_A

Get enumerated values variant

pub fn is_rtc_xtal_source_0(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_0

pub fn is_rtc_xtal_source_1(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_1

impl R<u32, Reg<u32, _MISC0_SET>>

pub fn reftop_pwd(&self) -> REFTOP_PWD_R

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&self) -> REFTOP_SELFBIASOFF_R

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&self) -> REFTOP_VBGADJ_R

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&self) -> REFTOP_VBGUP_R

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&self) -> STOP_MODE_CONFIG_R

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&self) -> DISCON_HIGH_SNVS_R

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&self) -> OSC_I_R

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok(&self) -> OSC_XTALOK_R

Bit 15 - Status bit that signals that the output of the 24-MHz crystal oscillator is stable

pub fn osc_xtalok_en(&self) -> OSC_XTALOK_EN_R

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&self) -> CLKGATE_CTRL_R

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&self) -> CLKGATE_DELAY_R

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&self) -> RTC_XTAL_SOURCE_R

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&self) -> XTAL_24M_PWD_R

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl R<bool, REFTOP_SELFBIASOFF_A>

pub fn variant(&self) -> REFTOP_SELFBIASOFF_A

Get enumerated values variant

pub fn is_reftop_selfbiasoff_0(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_0

pub fn is_reftop_selfbiasoff_1(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_1

impl R<u8, REFTOP_VBGADJ_A>

pub fn variant(&self) -> REFTOP_VBGADJ_A

Get enumerated values variant

pub fn is_reftop_vbgadj_0(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_0

pub fn is_reftop_vbgadj_1(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_1

pub fn is_reftop_vbgadj_2(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_2

pub fn is_reftop_vbgadj_3(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_3

pub fn is_reftop_vbgadj_4(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_4

pub fn is_reftop_vbgadj_5(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_5

pub fn is_reftop_vbgadj_6(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_6

pub fn is_reftop_vbgadj_7(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_7

impl R<u8, STOP_MODE_CONFIG_A>

pub fn variant(&self) -> STOP_MODE_CONFIG_A

Get enumerated values variant

pub fn is_stop_mode_config_0(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_0

pub fn is_stop_mode_config_1(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_1

pub fn is_stop_mode_config_2(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_2

pub fn is_stop_mode_config_3(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_3

impl R<bool, DISCON_HIGH_SNVS_A>

pub fn variant(&self) -> DISCON_HIGH_SNVS_A

Get enumerated values variant

pub fn is_discon_high_snvs_0(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_0

pub fn is_discon_high_snvs_1(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_1

impl R<u8, OSC_I_A>

pub fn variant(&self) -> OSC_I_A

Get enumerated values variant

pub fn is_nominal(&self) -> bool

Checks if the value of the field is NOMINAL

pub fn is_minus_12_5_percent(&self) -> bool

Checks if the value of the field is MINUS_12_5_PERCENT

pub fn is_minus_25_percent(&self) -> bool

Checks if the value of the field is MINUS_25_PERCENT

pub fn is_minus_37_5_percent(&self) -> bool

Checks if the value of the field is MINUS_37_5_PERCENT

impl R<bool, CLKGATE_CTRL_A>

pub fn variant(&self) -> CLKGATE_CTRL_A

Get enumerated values variant

pub fn is_allow_auto_gate(&self) -> bool

Checks if the value of the field is ALLOW_AUTO_GATE

pub fn is_no_auto_gate(&self) -> bool

Checks if the value of the field is NO_AUTO_GATE

impl R<u8, CLKGATE_DELAY_A>

pub fn variant(&self) -> CLKGATE_DELAY_A

Get enumerated values variant

pub fn is_clkgate_delay_0(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_0

pub fn is_clkgate_delay_1(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_1

pub fn is_clkgate_delay_2(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_2

pub fn is_clkgate_delay_3(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_3

pub fn is_clkgate_delay_4(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_4

pub fn is_clkgate_delay_5(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_5

pub fn is_clkgate_delay_6(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_6

pub fn is_clkgate_delay_7(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_7

impl R<bool, RTC_XTAL_SOURCE_A>

pub fn variant(&self) -> RTC_XTAL_SOURCE_A

Get enumerated values variant

pub fn is_rtc_xtal_source_0(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_0

pub fn is_rtc_xtal_source_1(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_1

impl R<u32, Reg<u32, _MISC0_CLR>>

pub fn reftop_pwd(&self) -> REFTOP_PWD_R

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&self) -> REFTOP_SELFBIASOFF_R

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&self) -> REFTOP_VBGADJ_R

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&self) -> REFTOP_VBGUP_R

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&self) -> STOP_MODE_CONFIG_R

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&self) -> DISCON_HIGH_SNVS_R

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&self) -> OSC_I_R

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok(&self) -> OSC_XTALOK_R

Bit 15 - Status bit that signals that the output of the 24-MHz crystal oscillator is stable

pub fn osc_xtalok_en(&self) -> OSC_XTALOK_EN_R

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&self) -> CLKGATE_CTRL_R

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&self) -> CLKGATE_DELAY_R

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&self) -> RTC_XTAL_SOURCE_R

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&self) -> XTAL_24M_PWD_R

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl R<bool, REFTOP_SELFBIASOFF_A>

pub fn variant(&self) -> REFTOP_SELFBIASOFF_A

Get enumerated values variant

pub fn is_reftop_selfbiasoff_0(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_0

pub fn is_reftop_selfbiasoff_1(&self) -> bool

Checks if the value of the field is REFTOP_SELFBIASOFF_1

impl R<u8, REFTOP_VBGADJ_A>

pub fn variant(&self) -> REFTOP_VBGADJ_A

Get enumerated values variant

pub fn is_reftop_vbgadj_0(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_0

pub fn is_reftop_vbgadj_1(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_1

pub fn is_reftop_vbgadj_2(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_2

pub fn is_reftop_vbgadj_3(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_3

pub fn is_reftop_vbgadj_4(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_4

pub fn is_reftop_vbgadj_5(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_5

pub fn is_reftop_vbgadj_6(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_6

pub fn is_reftop_vbgadj_7(&self) -> bool

Checks if the value of the field is REFTOP_VBGADJ_7

impl R<u8, STOP_MODE_CONFIG_A>

pub fn variant(&self) -> STOP_MODE_CONFIG_A

Get enumerated values variant

pub fn is_stop_mode_config_0(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_0

pub fn is_stop_mode_config_1(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_1

pub fn is_stop_mode_config_2(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_2

pub fn is_stop_mode_config_3(&self) -> bool

Checks if the value of the field is STOP_MODE_CONFIG_3

impl R<bool, DISCON_HIGH_SNVS_A>

pub fn variant(&self) -> DISCON_HIGH_SNVS_A

Get enumerated values variant

pub fn is_discon_high_snvs_0(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_0

pub fn is_discon_high_snvs_1(&self) -> bool

Checks if the value of the field is DISCON_HIGH_SNVS_1

impl R<u8, OSC_I_A>

pub fn variant(&self) -> OSC_I_A

Get enumerated values variant

pub fn is_nominal(&self) -> bool

Checks if the value of the field is NOMINAL

pub fn is_minus_12_5_percent(&self) -> bool

Checks if the value of the field is MINUS_12_5_PERCENT

pub fn is_minus_25_percent(&self) -> bool

Checks if the value of the field is MINUS_25_PERCENT

pub fn is_minus_37_5_percent(&self) -> bool

Checks if the value of the field is MINUS_37_5_PERCENT

impl R<bool, CLKGATE_CTRL_A>

pub fn variant(&self) -> CLKGATE_CTRL_A

Get enumerated values variant

pub fn is_allow_auto_gate(&self) -> bool

Checks if the value of the field is ALLOW_AUTO_GATE

pub fn is_no_auto_gate(&self) -> bool

Checks if the value of the field is NO_AUTO_GATE

impl R<u8, CLKGATE_DELAY_A>

pub fn variant(&self) -> CLKGATE_DELAY_A

Get enumerated values variant

pub fn is_clkgate_delay_0(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_0

pub fn is_clkgate_delay_1(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_1

pub fn is_clkgate_delay_2(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_2

pub fn is_clkgate_delay_3(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_3

pub fn is_clkgate_delay_4(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_4

pub fn is_clkgate_delay_5(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_5

pub fn is_clkgate_delay_6(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_6

pub fn is_clkgate_delay_7(&self) -> bool

Checks if the value of the field is CLKGATE_DELAY_7

impl R<bool, RTC_XTAL_SOURCE_A>

pub fn variant(&self) -> RTC_XTAL_SOURCE_A

Get enumerated values variant

pub fn is_rtc_xtal_source_0(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_0

pub fn is_rtc_xtal_source_1(&self) -> bool

Checks if the value of the field is RTC_XTAL_SOURCE_1

impl R<u32, Reg<u32, _MISC0_TOG>>

pub fn reftop_pwd(&self) -> REFTOP_PWD_R

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&self) -> REFTOP_SELFBIASOFF_R

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&self) -> REFTOP_VBGADJ_R

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&self) -> REFTOP_VBGUP_R

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&self) -> STOP_MODE_CONFIG_R

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&self) -> DISCON_HIGH_SNVS_R

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&self) -> OSC_I_R

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok(&self) -> OSC_XTALOK_R

Bit 15 - Status bit that signals that the output of the 24-MHz crystal oscillator is stable

pub fn osc_xtalok_en(&self) -> OSC_XTALOK_EN_R

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&self) -> CLKGATE_CTRL_R

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&self) -> CLKGATE_DELAY_R

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&self) -> RTC_XTAL_SOURCE_R

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&self) -> XTAL_24M_PWD_R

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl R<u8, LVDS1_CLK_SEL_A>

pub fn variant(&self) -> Variant<u8, LVDS1_CLK_SEL_A>

Get enumerated values variant

pub fn is_arm_pll(&self) -> bool

Checks if the value of the field is ARM_PLL

pub fn is_sys_pll(&self) -> bool

Checks if the value of the field is SYS_PLL

pub fn is_pfd4(&self) -> bool

Checks if the value of the field is PFD4

pub fn is_pfd5(&self) -> bool

Checks if the value of the field is PFD5

pub fn is_pfd6(&self) -> bool

Checks if the value of the field is PFD6

pub fn is_pfd7(&self) -> bool

Checks if the value of the field is PFD7

pub fn is_audio_pll(&self) -> bool

Checks if the value of the field is AUDIO_PLL

pub fn is_video_pll(&self) -> bool

Checks if the value of the field is VIDEO_PLL

pub fn is_ethernet_ref(&self) -> bool

Checks if the value of the field is ETHERNET_REF

pub fn is_usb1_pll(&self) -> bool

Checks if the value of the field is USB1_PLL

pub fn is_usb2_pll(&self) -> bool

Checks if the value of the field is USB2_PLL

pub fn is_pfd0(&self) -> bool

Checks if the value of the field is PFD0

pub fn is_pfd1(&self) -> bool

Checks if the value of the field is PFD1

pub fn is_pfd2(&self) -> bool

Checks if the value of the field is PFD2

pub fn is_pfd3(&self) -> bool

Checks if the value of the field is PFD3

pub fn is_xtal(&self) -> bool

Checks if the value of the field is XTAL

impl R<u32, Reg<u32, _MISC1>>

pub fn lvds1_clk_sel(&self) -> LVDS1_CLK_SEL_R

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&self) -> LVDSCLK1_OBEN_R

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&self) -> LVDSCLK1_IBEN_R

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&self) -> PFD_480_AUTOGATE_EN_R

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&self) -> PFD_528_AUTOGATE_EN_R

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&self) -> IRQ_TEMPPANIC_R

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&self) -> IRQ_TEMPLOW_R

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&self) -> IRQ_TEMPHIGH_R

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&self) -> IRQ_ANA_BO_R

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&self) -> IRQ_DIG_BO_R

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl R<u8, LVDS1_CLK_SEL_A>

pub fn variant(&self) -> Variant<u8, LVDS1_CLK_SEL_A>

Get enumerated values variant

pub fn is_arm_pll(&self) -> bool

Checks if the value of the field is ARM_PLL

pub fn is_sys_pll(&self) -> bool

Checks if the value of the field is SYS_PLL

pub fn is_pfd4(&self) -> bool

Checks if the value of the field is PFD4

pub fn is_pfd5(&self) -> bool

Checks if the value of the field is PFD5

pub fn is_pfd6(&self) -> bool

Checks if the value of the field is PFD6

pub fn is_pfd7(&self) -> bool

Checks if the value of the field is PFD7

pub fn is_audio_pll(&self) -> bool

Checks if the value of the field is AUDIO_PLL

pub fn is_video_pll(&self) -> bool

Checks if the value of the field is VIDEO_PLL

pub fn is_ethernet_ref(&self) -> bool

Checks if the value of the field is ETHERNET_REF

pub fn is_usb1_pll(&self) -> bool

Checks if the value of the field is USB1_PLL

pub fn is_usb2_pll(&self) -> bool

Checks if the value of the field is USB2_PLL

pub fn is_pfd0(&self) -> bool

Checks if the value of the field is PFD0

pub fn is_pfd1(&self) -> bool

Checks if the value of the field is PFD1

pub fn is_pfd2(&self) -> bool

Checks if the value of the field is PFD2

pub fn is_pfd3(&self) -> bool

Checks if the value of the field is PFD3

pub fn is_xtal(&self) -> bool

Checks if the value of the field is XTAL

impl R<u32, Reg<u32, _MISC1_SET>>

pub fn lvds1_clk_sel(&self) -> LVDS1_CLK_SEL_R

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&self) -> LVDSCLK1_OBEN_R

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&self) -> LVDSCLK1_IBEN_R

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&self) -> PFD_480_AUTOGATE_EN_R

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&self) -> PFD_528_AUTOGATE_EN_R

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&self) -> IRQ_TEMPPANIC_R

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&self) -> IRQ_TEMPLOW_R

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&self) -> IRQ_TEMPHIGH_R

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&self) -> IRQ_ANA_BO_R

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&self) -> IRQ_DIG_BO_R

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl R<u8, LVDS1_CLK_SEL_A>

pub fn variant(&self) -> Variant<u8, LVDS1_CLK_SEL_A>

Get enumerated values variant

pub fn is_arm_pll(&self) -> bool

Checks if the value of the field is ARM_PLL

pub fn is_sys_pll(&self) -> bool

Checks if the value of the field is SYS_PLL

pub fn is_pfd4(&self) -> bool

Checks if the value of the field is PFD4

pub fn is_pfd5(&self) -> bool

Checks if the value of the field is PFD5

pub fn is_pfd6(&self) -> bool

Checks if the value of the field is PFD6

pub fn is_pfd7(&self) -> bool

Checks if the value of the field is PFD7

pub fn is_audio_pll(&self) -> bool

Checks if the value of the field is AUDIO_PLL

pub fn is_video_pll(&self) -> bool

Checks if the value of the field is VIDEO_PLL

pub fn is_ethernet_ref(&self) -> bool

Checks if the value of the field is ETHERNET_REF

pub fn is_usb1_pll(&self) -> bool

Checks if the value of the field is USB1_PLL

pub fn is_usb2_pll(&self) -> bool

Checks if the value of the field is USB2_PLL

pub fn is_pfd0(&self) -> bool

Checks if the value of the field is PFD0

pub fn is_pfd1(&self) -> bool

Checks if the value of the field is PFD1

pub fn is_pfd2(&self) -> bool

Checks if the value of the field is PFD2

pub fn is_pfd3(&self) -> bool

Checks if the value of the field is PFD3

pub fn is_xtal(&self) -> bool

Checks if the value of the field is XTAL

impl R<u32, Reg<u32, _MISC1_CLR>>

pub fn lvds1_clk_sel(&self) -> LVDS1_CLK_SEL_R

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&self) -> LVDSCLK1_OBEN_R

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&self) -> LVDSCLK1_IBEN_R

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&self) -> PFD_480_AUTOGATE_EN_R

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&self) -> PFD_528_AUTOGATE_EN_R

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&self) -> IRQ_TEMPPANIC_R

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&self) -> IRQ_TEMPLOW_R

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&self) -> IRQ_TEMPHIGH_R

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&self) -> IRQ_ANA_BO_R

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&self) -> IRQ_DIG_BO_R

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl R<u8, LVDS1_CLK_SEL_A>

pub fn variant(&self) -> Variant<u8, LVDS1_CLK_SEL_A>

Get enumerated values variant

pub fn is_arm_pll(&self) -> bool

Checks if the value of the field is ARM_PLL

pub fn is_sys_pll(&self) -> bool

Checks if the value of the field is SYS_PLL

pub fn is_pfd4(&self) -> bool

Checks if the value of the field is PFD4

pub fn is_pfd5(&self) -> bool

Checks if the value of the field is PFD5

pub fn is_pfd6(&self) -> bool

Checks if the value of the field is PFD6

pub fn is_pfd7(&self) -> bool

Checks if the value of the field is PFD7

pub fn is_audio_pll(&self) -> bool

Checks if the value of the field is AUDIO_PLL

pub fn is_video_pll(&self) -> bool

Checks if the value of the field is VIDEO_PLL

pub fn is_ethernet_ref(&self) -> bool

Checks if the value of the field is ETHERNET_REF

pub fn is_usb1_pll(&self) -> bool

Checks if the value of the field is USB1_PLL

pub fn is_usb2_pll(&self) -> bool

Checks if the value of the field is USB2_PLL

pub fn is_pfd0(&self) -> bool

Checks if the value of the field is PFD0

pub fn is_pfd1(&self) -> bool

Checks if the value of the field is PFD1

pub fn is_pfd2(&self) -> bool

Checks if the value of the field is PFD2

pub fn is_pfd3(&self) -> bool

Checks if the value of the field is PFD3

pub fn is_xtal(&self) -> bool

Checks if the value of the field is XTAL

impl R<u32, Reg<u32, _MISC1_TOG>>

pub fn lvds1_clk_sel(&self) -> LVDS1_CLK_SEL_R

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&self) -> LVDSCLK1_OBEN_R

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&self) -> LVDSCLK1_IBEN_R

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&self) -> PFD_480_AUTOGATE_EN_R

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&self) -> PFD_528_AUTOGATE_EN_R

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&self) -> IRQ_TEMPPANIC_R

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&self) -> IRQ_TEMPLOW_R

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&self) -> IRQ_TEMPHIGH_R

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&self) -> IRQ_ANA_BO_R

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&self) -> IRQ_DIG_BO_R

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl R<u8, REG0_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG0_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg0_bo_offset_4(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_4

pub fn is_reg0_bo_offset_7(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_7

impl R<bool, REG0_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG0_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg0_bo_status_1(&self) -> bool

Checks if the value of the field is REG0_BO_STATUS_1

impl R<bool, PLL3_DISABLE_A>

pub fn variant(&self) -> PLL3_DISABLE_A

Get enumerated values variant

pub fn is_pll3_disable_0(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_0

pub fn is_pll3_disable_1(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_1

impl R<u8, REG1_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG1_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg1_bo_offset_4(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_4

pub fn is_reg1_bo_offset_7(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_7

impl R<bool, REG1_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG1_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg1_bo_status_1(&self) -> bool

Checks if the value of the field is REG1_BO_STATUS_1

impl R<bool, AUDIO_DIV_LSB_A>

pub fn variant(&self) -> AUDIO_DIV_LSB_A

Get enumerated values variant

pub fn is_audio_div_lsb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_0

pub fn is_audio_div_lsb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_1

impl R<u8, REG2_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG2_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg2_bo_offset_4(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_4

pub fn is_reg2_bo_offset_7(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_7

impl R<bool, AUDIO_DIV_MSB_A>

pub fn variant(&self) -> AUDIO_DIV_MSB_A

Get enumerated values variant

pub fn is_audio_div_msb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_0

pub fn is_audio_div_msb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_1

impl R<u8, REG0_STEP_TIME_A>

pub fn variant(&self) -> REG0_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG1_STEP_TIME_A>

pub fn variant(&self) -> REG1_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG2_STEP_TIME_A>

pub fn variant(&self) -> REG2_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, VIDEO_DIV_A>

pub fn variant(&self) -> VIDEO_DIV_A

Get enumerated values variant

pub fn is_video_div_0(&self) -> bool

Checks if the value of the field is VIDEO_DIV_0

pub fn is_video_div_1(&self) -> bool

Checks if the value of the field is VIDEO_DIV_1

pub fn is_video_div_2(&self) -> bool

Checks if the value of the field is VIDEO_DIV_2

pub fn is_video_div_3(&self) -> bool

Checks if the value of the field is VIDEO_DIV_3

impl R<u32, Reg<u32, _MISC2>>

pub fn reg0_bo_offset(&self) -> REG0_BO_OFFSET_R

Bits 0:2 - This field defines the brown out voltage offset for the CORE power domain

pub fn reg0_bo_status(&self) -> REG0_BO_STATUS_R

Bit 3 - Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_enable_bo(&self) -> REG0_ENABLE_BO_R

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_ok(&self) -> REG0_OK_R

Bit 6 - ARM supply Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&self) -> PLL3_DISABLE_R

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_bo_offset(&self) -> REG1_BO_OFFSET_R

Bits 8:10 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg1_bo_status(&self) -> REG1_BO_STATUS_R

Bit 11 - Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_enable_bo(&self) -> REG1_ENABLE_BO_R

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_ok(&self) -> REG1_OK_R

Bit 14 - GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&self) -> AUDIO_DIV_LSB_R

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_bo_offset(&self) -> REG2_BO_OFFSET_R

Bits 16:18 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg2_bo_status(&self) -> REG2_BO_STATUS_R

Bit 19 - Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_enable_bo(&self) -> REG2_ENABLE_BO_R

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_ok(&self) -> REG2_OK_R

Bit 22 - Signals that the voltage is above the brownout level for the SOC supply

pub fn audio_div_msb(&self) -> AUDIO_DIV_MSB_R

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&self) -> REG0_STEP_TIME_R

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&self) -> REG1_STEP_TIME_R

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&self) -> REG2_STEP_TIME_R

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&self) -> VIDEO_DIV_R

Bits 30:31 - Post-divider for video

impl R<u8, REG0_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG0_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg0_bo_offset_4(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_4

pub fn is_reg0_bo_offset_7(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_7

impl R<bool, REG0_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG0_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg0_bo_status_1(&self) -> bool

Checks if the value of the field is REG0_BO_STATUS_1

impl R<bool, PLL3_DISABLE_A>

pub fn variant(&self) -> PLL3_DISABLE_A

Get enumerated values variant

pub fn is_pll3_disable_0(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_0

pub fn is_pll3_disable_1(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_1

impl R<u8, REG1_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG1_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg1_bo_offset_4(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_4

pub fn is_reg1_bo_offset_7(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_7

impl R<bool, REG1_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG1_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg1_bo_status_1(&self) -> bool

Checks if the value of the field is REG1_BO_STATUS_1

impl R<bool, AUDIO_DIV_LSB_A>

pub fn variant(&self) -> AUDIO_DIV_LSB_A

Get enumerated values variant

pub fn is_audio_div_lsb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_0

pub fn is_audio_div_lsb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_1

impl R<u8, REG2_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG2_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg2_bo_offset_4(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_4

pub fn is_reg2_bo_offset_7(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_7

impl R<bool, AUDIO_DIV_MSB_A>

pub fn variant(&self) -> AUDIO_DIV_MSB_A

Get enumerated values variant

pub fn is_audio_div_msb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_0

pub fn is_audio_div_msb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_1

impl R<u8, REG0_STEP_TIME_A>

pub fn variant(&self) -> REG0_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG1_STEP_TIME_A>

pub fn variant(&self) -> REG1_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG2_STEP_TIME_A>

pub fn variant(&self) -> REG2_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, VIDEO_DIV_A>

pub fn variant(&self) -> VIDEO_DIV_A

Get enumerated values variant

pub fn is_video_div_0(&self) -> bool

Checks if the value of the field is VIDEO_DIV_0

pub fn is_video_div_1(&self) -> bool

Checks if the value of the field is VIDEO_DIV_1

pub fn is_video_div_2(&self) -> bool

Checks if the value of the field is VIDEO_DIV_2

pub fn is_video_div_3(&self) -> bool

Checks if the value of the field is VIDEO_DIV_3

impl R<u32, Reg<u32, _MISC2_SET>>

pub fn reg0_bo_offset(&self) -> REG0_BO_OFFSET_R

Bits 0:2 - This field defines the brown out voltage offset for the CORE power domain

pub fn reg0_bo_status(&self) -> REG0_BO_STATUS_R

Bit 3 - Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_enable_bo(&self) -> REG0_ENABLE_BO_R

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_ok(&self) -> REG0_OK_R

Bit 6 - ARM supply Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&self) -> PLL3_DISABLE_R

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_bo_offset(&self) -> REG1_BO_OFFSET_R

Bits 8:10 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg1_bo_status(&self) -> REG1_BO_STATUS_R

Bit 11 - Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_enable_bo(&self) -> REG1_ENABLE_BO_R

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_ok(&self) -> REG1_OK_R

Bit 14 - GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&self) -> AUDIO_DIV_LSB_R

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_bo_offset(&self) -> REG2_BO_OFFSET_R

Bits 16:18 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg2_bo_status(&self) -> REG2_BO_STATUS_R

Bit 19 - Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_enable_bo(&self) -> REG2_ENABLE_BO_R

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_ok(&self) -> REG2_OK_R

Bit 22 - Signals that the voltage is above the brownout level for the SOC supply

pub fn audio_div_msb(&self) -> AUDIO_DIV_MSB_R

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&self) -> REG0_STEP_TIME_R

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&self) -> REG1_STEP_TIME_R

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&self) -> REG2_STEP_TIME_R

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&self) -> VIDEO_DIV_R

Bits 30:31 - Post-divider for video

impl R<u8, REG0_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG0_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg0_bo_offset_4(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_4

pub fn is_reg0_bo_offset_7(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_7

impl R<bool, REG0_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG0_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg0_bo_status_1(&self) -> bool

Checks if the value of the field is REG0_BO_STATUS_1

impl R<bool, PLL3_DISABLE_A>

pub fn variant(&self) -> PLL3_DISABLE_A

Get enumerated values variant

pub fn is_pll3_disable_0(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_0

pub fn is_pll3_disable_1(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_1

impl R<u8, REG1_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG1_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg1_bo_offset_4(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_4

pub fn is_reg1_bo_offset_7(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_7

impl R<bool, REG1_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG1_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg1_bo_status_1(&self) -> bool

Checks if the value of the field is REG1_BO_STATUS_1

impl R<bool, AUDIO_DIV_LSB_A>

pub fn variant(&self) -> AUDIO_DIV_LSB_A

Get enumerated values variant

pub fn is_audio_div_lsb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_0

pub fn is_audio_div_lsb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_1

impl R<u8, REG2_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG2_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg2_bo_offset_4(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_4

pub fn is_reg2_bo_offset_7(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_7

impl R<bool, AUDIO_DIV_MSB_A>

pub fn variant(&self) -> AUDIO_DIV_MSB_A

Get enumerated values variant

pub fn is_audio_div_msb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_0

pub fn is_audio_div_msb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_1

impl R<u8, REG0_STEP_TIME_A>

pub fn variant(&self) -> REG0_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG1_STEP_TIME_A>

pub fn variant(&self) -> REG1_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG2_STEP_TIME_A>

pub fn variant(&self) -> REG2_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, VIDEO_DIV_A>

pub fn variant(&self) -> VIDEO_DIV_A

Get enumerated values variant

pub fn is_video_div_0(&self) -> bool

Checks if the value of the field is VIDEO_DIV_0

pub fn is_video_div_1(&self) -> bool

Checks if the value of the field is VIDEO_DIV_1

pub fn is_video_div_2(&self) -> bool

Checks if the value of the field is VIDEO_DIV_2

pub fn is_video_div_3(&self) -> bool

Checks if the value of the field is VIDEO_DIV_3

impl R<u32, Reg<u32, _MISC2_CLR>>

pub fn reg0_bo_offset(&self) -> REG0_BO_OFFSET_R

Bits 0:2 - This field defines the brown out voltage offset for the CORE power domain

pub fn reg0_bo_status(&self) -> REG0_BO_STATUS_R

Bit 3 - Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_enable_bo(&self) -> REG0_ENABLE_BO_R

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_ok(&self) -> REG0_OK_R

Bit 6 - ARM supply Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&self) -> PLL3_DISABLE_R

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_bo_offset(&self) -> REG1_BO_OFFSET_R

Bits 8:10 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg1_bo_status(&self) -> REG1_BO_STATUS_R

Bit 11 - Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_enable_bo(&self) -> REG1_ENABLE_BO_R

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_ok(&self) -> REG1_OK_R

Bit 14 - GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&self) -> AUDIO_DIV_LSB_R

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_bo_offset(&self) -> REG2_BO_OFFSET_R

Bits 16:18 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg2_bo_status(&self) -> REG2_BO_STATUS_R

Bit 19 - Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_enable_bo(&self) -> REG2_ENABLE_BO_R

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_ok(&self) -> REG2_OK_R

Bit 22 - Signals that the voltage is above the brownout level for the SOC supply

pub fn audio_div_msb(&self) -> AUDIO_DIV_MSB_R

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&self) -> REG0_STEP_TIME_R

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&self) -> REG1_STEP_TIME_R

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&self) -> REG2_STEP_TIME_R

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&self) -> VIDEO_DIV_R

Bits 30:31 - Post-divider for video

impl R<u8, REG0_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG0_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg0_bo_offset_4(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_4

pub fn is_reg0_bo_offset_7(&self) -> bool

Checks if the value of the field is REG0_BO_OFFSET_7

impl R<bool, REG0_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG0_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg0_bo_status_1(&self) -> bool

Checks if the value of the field is REG0_BO_STATUS_1

impl R<bool, PLL3_DISABLE_A>

pub fn variant(&self) -> PLL3_DISABLE_A

Get enumerated values variant

pub fn is_pll3_disable_0(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_0

pub fn is_pll3_disable_1(&self) -> bool

Checks if the value of the field is PLL3_DISABLE_1

impl R<u8, REG1_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG1_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg1_bo_offset_4(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_4

pub fn is_reg1_bo_offset_7(&self) -> bool

Checks if the value of the field is REG1_BO_OFFSET_7

impl R<bool, REG1_BO_STATUS_A>

pub fn variant(&self) -> Variant<bool, REG1_BO_STATUS_A>

Get enumerated values variant

pub fn is_reg1_bo_status_1(&self) -> bool

Checks if the value of the field is REG1_BO_STATUS_1

impl R<bool, AUDIO_DIV_LSB_A>

pub fn variant(&self) -> AUDIO_DIV_LSB_A

Get enumerated values variant

pub fn is_audio_div_lsb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_0

pub fn is_audio_div_lsb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_LSB_1

impl R<u8, REG2_BO_OFFSET_A>

pub fn variant(&self) -> Variant<u8, REG2_BO_OFFSET_A>

Get enumerated values variant

pub fn is_reg2_bo_offset_4(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_4

pub fn is_reg2_bo_offset_7(&self) -> bool

Checks if the value of the field is REG2_BO_OFFSET_7

impl R<bool, AUDIO_DIV_MSB_A>

pub fn variant(&self) -> AUDIO_DIV_MSB_A

Get enumerated values variant

pub fn is_audio_div_msb_0(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_0

pub fn is_audio_div_msb_1(&self) -> bool

Checks if the value of the field is AUDIO_DIV_MSB_1

impl R<u8, REG0_STEP_TIME_A>

pub fn variant(&self) -> REG0_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG1_STEP_TIME_A>

pub fn variant(&self) -> REG1_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, REG2_STEP_TIME_A>

pub fn variant(&self) -> REG2_STEP_TIME_A

Get enumerated values variant

pub fn is_64_clocks(&self) -> bool

Checks if the value of the field is _64_CLOCKS

pub fn is_128_clocks(&self) -> bool

Checks if the value of the field is _128_CLOCKS

pub fn is_256_clocks(&self) -> bool

Checks if the value of the field is _256_CLOCKS

pub fn is_512_clocks(&self) -> bool

Checks if the value of the field is _512_CLOCKS

impl R<u8, VIDEO_DIV_A>

pub fn variant(&self) -> VIDEO_DIV_A

Get enumerated values variant

pub fn is_video_div_0(&self) -> bool

Checks if the value of the field is VIDEO_DIV_0

pub fn is_video_div_1(&self) -> bool

Checks if the value of the field is VIDEO_DIV_1

pub fn is_video_div_2(&self) -> bool

Checks if the value of the field is VIDEO_DIV_2

pub fn is_video_div_3(&self) -> bool

Checks if the value of the field is VIDEO_DIV_3

impl R<u32, Reg<u32, _MISC2_TOG>>

pub fn reg0_bo_offset(&self) -> REG0_BO_OFFSET_R

Bits 0:2 - This field defines the brown out voltage offset for the CORE power domain

pub fn reg0_bo_status(&self) -> REG0_BO_STATUS_R

Bit 3 - Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_enable_bo(&self) -> REG0_ENABLE_BO_R

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg0_ok(&self) -> REG0_OK_R

Bit 6 - ARM supply Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&self) -> PLL3_DISABLE_R

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_bo_offset(&self) -> REG1_BO_OFFSET_R

Bits 8:10 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg1_bo_status(&self) -> REG1_BO_STATUS_R

Bit 11 - Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_enable_bo(&self) -> REG1_ENABLE_BO_R

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_ok(&self) -> REG1_OK_R

Bit 14 - GPU/VPU supply Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&self) -> AUDIO_DIV_LSB_R

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_bo_offset(&self) -> REG2_BO_OFFSET_R

Bits 16:18 - This field defines the brown out voltage offset for the xPU power domain

pub fn reg2_bo_status(&self) -> REG2_BO_STATUS_R

Bit 19 - Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_enable_bo(&self) -> REG2_ENABLE_BO_R

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_ok(&self) -> REG2_OK_R

Bit 22 - Signals that the voltage is above the brownout level for the SOC supply

pub fn audio_div_msb(&self) -> AUDIO_DIV_MSB_R

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&self) -> REG0_STEP_TIME_R

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&self) -> REG1_STEP_TIME_R

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&self) -> REG2_STEP_TIME_R

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&self) -> VIDEO_DIV_R

Bits 30:31 - Post-divider for video

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 

fn eq(&self, other: &FI) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.