[][src]Type Definition imxrt1062_ccm_analog::misc0_clr::W

type W = W<u32, MISC0_CLR>;

Writer for register MISC0_CLR

Methods

impl W[src]

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W[src]

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W[src]

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W[src]

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W[src]

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W[src]

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W[src]

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W[src]

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W[src]

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W[src]

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W[src]

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&mut self) -> RTC_XTAL_SOURCE_W[src]

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W[src]

Bit 30 - This field powers down the 24M crystal oscillator if set true