[−][src]Struct imxrt1062_adc_etc::R
Register/field reader
Result of the read
method of a register.
Also it can be used in the modify
method
Methods
impl<U, T> R<U, T> where
U: Copy,
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U: Copy,
impl<FI> R<bool, FI>
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pub fn bit(&self) -> bool
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Value of the field as raw bits
pub fn bit_is_clear(&self) -> bool
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Returns true
if the bit is clear (0)
pub fn bit_is_set(&self) -> bool
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Returns true
if the bit is set (1)
impl R<u32, Reg<u32, _CTRL>>
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pub fn trig_enable(&self) -> TRIG_ENABLE_R
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Bits 0:7 - TRIG enable register
pub fn ext0_trig_enable(&self) -> EXT0_TRIG_ENABLE_R
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Bit 8 - TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger.
pub fn ext0_trig_priority(&self) -> EXT0_TRIG_PRIORITY_R
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Bits 9:11 - External TSC0 trigger priority, 7 is Highest, 0 is lowest .
pub fn ext1_trig_enable(&self) -> EXT1_TRIG_ENABLE_R
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Bit 12 - TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger.
pub fn ext1_trig_priority(&self) -> EXT1_TRIG_PRIORITY_R
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Bits 13:15 - External TSC1 trigger priority, 7 is Highest, 0 is lowest .
pub fn pre_divider(&self) -> PRE_DIVIDER_R
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Bits 16:23 - Pre-divider for trig delay and interval .
pub fn dma_mode_sel(&self) -> DMA_MODE_SEL_R
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Bit 29 - 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared
pub fn tsc_bypass(&self) -> TSC_BYPASS_R
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Bit 30 - 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared.
pub fn softrst(&self) -> SOFTRST_R
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Bit 31 - Software reset, high active. When write 1 ,all logical will be reset.
impl R<u32, Reg<u32, _DONE0_1_IRQ>>
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pub fn trig0_done0(&self) -> TRIG0_DONE0_R
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Bit 0 - TRIG0 done0 interrupt detection
pub fn trig1_done0(&self) -> TRIG1_DONE0_R
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Bit 1 - TRIG1 done0 interrupt detection
pub fn trig2_done0(&self) -> TRIG2_DONE0_R
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Bit 2 - TRIG2 done0 interrupt detection
pub fn trig3_done0(&self) -> TRIG3_DONE0_R
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Bit 3 - TRIG3 done0 interrupt detection
pub fn trig4_done0(&self) -> TRIG4_DONE0_R
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Bit 4 - TRIG4 done0 interrupt detection
pub fn trig5_done0(&self) -> TRIG5_DONE0_R
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Bit 5 - TRIG5 done0 interrupt detection
pub fn trig6_done0(&self) -> TRIG6_DONE0_R
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Bit 6 - TRIG6 done0 interrupt detection
pub fn trig7_done0(&self) -> TRIG7_DONE0_R
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Bit 7 - TRIG7 done0 interrupt detection
pub fn trig0_done1(&self) -> TRIG0_DONE1_R
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Bit 16 - TRIG0 done1 interrupt detection
pub fn trig1_done1(&self) -> TRIG1_DONE1_R
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Bit 17 - TRIG1 done1 interrupt detection
pub fn trig2_done1(&self) -> TRIG2_DONE1_R
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Bit 18 - TRIG2 done1 interrupt detection
pub fn trig3_done1(&self) -> TRIG3_DONE1_R
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Bit 19 - TRIG3 done1 interrupt detection
pub fn trig4_done1(&self) -> TRIG4_DONE1_R
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Bit 20 - TRIG4 done1 interrupt detection
pub fn trig5_done1(&self) -> TRIG5_DONE1_R
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Bit 21 - TRIG5 done1 interrupt detection
pub fn trig6_done1(&self) -> TRIG6_DONE1_R
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Bit 22 - TRIG6 done1 interrupt detection
pub fn trig7_done1(&self) -> TRIG7_DONE1_R
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Bit 23 - TRIG7 done1 interrupt detection
impl R<u32, Reg<u32, _DONE2_ERR_IRQ>>
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pub fn trig0_done2(&self) -> TRIG0_DONE2_R
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Bit 0 - TRIG0 done2 interrupt detection
pub fn trig1_done2(&self) -> TRIG1_DONE2_R
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Bit 1 - TRIG1 done2 interrupt detection
pub fn trig2_done2(&self) -> TRIG2_DONE2_R
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Bit 2 - TRIG2 done2 interrupt detection
pub fn trig3_done2(&self) -> TRIG3_DONE2_R
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Bit 3 - TRIG3 done2 interrupt detection
pub fn trig4_done2(&self) -> TRIG4_DONE2_R
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Bit 4 - TRIG4 done2 interrupt detection
pub fn trig5_done2(&self) -> TRIG5_DONE2_R
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Bit 5 - TRIG5 done2 interrupt detection
pub fn trig6_done2(&self) -> TRIG6_DONE2_R
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Bit 6 - TRIG6 done2 interrupt detection
pub fn trig7_done2(&self) -> TRIG7_DONE2_R
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Bit 7 - TRIG7 done2 interrupt detection
pub fn trig0_err(&self) -> TRIG0_ERR_R
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Bit 16 - TRIG0 error interrupt detection
pub fn trig1_err(&self) -> TRIG1_ERR_R
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Bit 17 - TRIG1 error interrupt detection
pub fn trig2_err(&self) -> TRIG2_ERR_R
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Bit 18 - TRIG2 error interrupt detection
pub fn trig3_err(&self) -> TRIG3_ERR_R
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Bit 19 - TRIG3 error interrupt detection
pub fn trig4_err(&self) -> TRIG4_ERR_R
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Bit 20 - TRIG4 error interrupt detection
pub fn trig5_err(&self) -> TRIG5_ERR_R
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Bit 21 - TRIG5 error interrupt detection
pub fn trig6_err(&self) -> TRIG6_ERR_R
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Bit 22 - TRIG6 error interrupt detection
pub fn trig7_err(&self) -> TRIG7_ERR_R
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Bit 23 - TRIG7 error interrupt detection
impl R<u32, Reg<u32, _DMA_CTRL>>
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pub fn trig0_enable(&self) -> TRIG0_ENABLE_R
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Bit 0 - When TRIG0 done enable DMA request
pub fn trig1_enable(&self) -> TRIG1_ENABLE_R
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Bit 1 - When TRIG1 done enable DMA request
pub fn trig2_enable(&self) -> TRIG2_ENABLE_R
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Bit 2 - When TRIG2 done enable DMA request
pub fn trig3_enable(&self) -> TRIG3_ENABLE_R
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Bit 3 - When TRIG3 done enable DMA request
pub fn trig4_enable(&self) -> TRIG4_ENABLE_R
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Bit 4 - When TRIG4 done enable DMA request
pub fn trig5_enable(&self) -> TRIG5_ENABLE_R
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Bit 5 - When TRIG5 done enable DMA request
pub fn trig6_enable(&self) -> TRIG6_ENABLE_R
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Bit 6 - When TRIG6 done enable DMA request
pub fn trig7_enable(&self) -> TRIG7_ENABLE_R
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Bit 7 - When TRIG7 done enable DMA request
pub fn trig0_req(&self) -> TRIG0_REQ_R
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Bit 16 - When TRIG0 done DMA request detection
pub fn trig1_req(&self) -> TRIG1_REQ_R
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Bit 17 - When TRIG1 done DMA request detection
pub fn trig2_req(&self) -> TRIG2_REQ_R
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Bit 18 - When TRIG2 done DMA request detection
pub fn trig3_req(&self) -> TRIG3_REQ_R
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Bit 19 - When TRIG3 done DMA request detection
pub fn trig4_req(&self) -> TRIG4_REQ_R
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Bit 20 - When TRIG4 done DMA request detection
pub fn trig5_req(&self) -> TRIG5_REQ_R
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Bit 21 - When TRIG5 done DMA request detection
pub fn trig6_req(&self) -> TRIG6_REQ_R
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Bit 22 - When TRIG6 done DMA request detection
pub fn trig7_req(&self) -> TRIG7_REQ_R
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Bit 23 - When TRIG7 done DMA request detection
impl R<u32, Reg<u32, _TRIG0_CTRL>>
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pub fn sw_trig(&self) -> SW_TRIG_R
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Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
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Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
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Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
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Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
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Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG0_COUNTER>>
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pub fn init_delay(&self) -> INIT_DELAY_R
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Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
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Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG0_CHAIN_1_0>>
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pub fn csel0(&self) -> CSEL0_R
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Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
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Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
pub fn b2b0(&self) -> B2B0_R
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Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
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Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
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Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
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Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter.
pub fn b2b1(&self) -> B2B1_R
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Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
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Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG0_CHAIN_3_2>>
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pub fn csel2(&self) -> CSEL2_R
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Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
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Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
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Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
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Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
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Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
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Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
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Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
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Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG0_CHAIN_5_4>>
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pub fn csel4(&self) -> CSEL4_R
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Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
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Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
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Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
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Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
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Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
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Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
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Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
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Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG0_CHAIN_7_6>>
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pub fn csel6(&self) -> CSEL6_R
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Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
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Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
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Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
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Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
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Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
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Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
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Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
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Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG0_RESULT_1_0>>
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pub fn data0(&self) -> DATA0_R
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Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
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Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG0_RESULT_3_2>>
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pub fn data2(&self) -> DATA2_R
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Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
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Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG0_RESULT_5_4>>
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pub fn data4(&self) -> DATA4_R
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Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
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Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG0_RESULT_7_6>>
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pub fn data6(&self) -> DATA6_R
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Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
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Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG1_CTRL>>
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pub fn sw_trig(&self) -> SW_TRIG_R
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Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
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Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
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Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
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Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
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Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG1_COUNTER>>
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pub fn init_delay(&self) -> INIT_DELAY_R
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Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
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Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG1_CHAIN_1_0>>
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pub fn csel0(&self) -> CSEL0_R
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Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
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Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
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Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
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Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
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Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
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Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
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Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
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Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG1_CHAIN_3_2>>
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pub fn csel2(&self) -> CSEL2_R
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Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
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Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
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Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
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Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
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Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
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Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
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Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
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Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG1_CHAIN_5_4>>
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pub fn csel4(&self) -> CSEL4_R
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Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
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Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
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Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
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Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
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Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
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Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
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Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
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Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG1_CHAIN_7_6>>
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pub fn csel6(&self) -> CSEL6_R
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Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
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Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
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Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
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Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
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Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
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Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
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Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
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Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG1_RESULT_1_0>>
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pub fn data0(&self) -> DATA0_R
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Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
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Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG1_RESULT_3_2>>
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pub fn data2(&self) -> DATA2_R
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Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
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Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG1_RESULT_5_4>>
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pub fn data4(&self) -> DATA4_R
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Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
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Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG1_RESULT_7_6>>
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pub fn data6(&self) -> DATA6_R
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Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
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Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG2_CTRL>>
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pub fn sw_trig(&self) -> SW_TRIG_R
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Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
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Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
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Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
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Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
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Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG2_COUNTER>>
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pub fn init_delay(&self) -> INIT_DELAY_R
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Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
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Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG2_CHAIN_1_0>>
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pub fn csel0(&self) -> CSEL0_R
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Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
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Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
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Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
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Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
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Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
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Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
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Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
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Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG2_CHAIN_3_2>>
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pub fn csel2(&self) -> CSEL2_R
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Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
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Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
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Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
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Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
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Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
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Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
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Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
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Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG2_CHAIN_5_4>>
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pub fn csel4(&self) -> CSEL4_R
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Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
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Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
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Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
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Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
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Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
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Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
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Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
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Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG2_CHAIN_7_6>>
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pub fn csel6(&self) -> CSEL6_R
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Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
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Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG2_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG2_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG2_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG2_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG3_CTRL>>
[src]
pub fn sw_trig(&self) -> SW_TRIG_R
[src]
Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
[src]
Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
[src]
Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
[src]
Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
[src]
Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG3_COUNTER>>
[src]
pub fn init_delay(&self) -> INIT_DELAY_R
[src]
Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
[src]
Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG3_CHAIN_1_0>>
[src]
pub fn csel0(&self) -> CSEL0_R
[src]
Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
[src]
Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
[src]
Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
[src]
Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
[src]
Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
[src]
Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
[src]
Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
[src]
Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG3_CHAIN_3_2>>
[src]
pub fn csel2(&self) -> CSEL2_R
[src]
Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
[src]
Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
[src]
Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
[src]
Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
[src]
Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
[src]
Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
[src]
Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
[src]
Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG3_CHAIN_5_4>>
[src]
pub fn csel4(&self) -> CSEL4_R
[src]
Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
[src]
Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
[src]
Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
[src]
Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
[src]
Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
[src]
Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
[src]
Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
[src]
Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG3_CHAIN_7_6>>
[src]
pub fn csel6(&self) -> CSEL6_R
[src]
Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
[src]
Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG3_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG3_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG3_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG3_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG4_CTRL>>
[src]
pub fn sw_trig(&self) -> SW_TRIG_R
[src]
Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
[src]
Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
[src]
Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
[src]
Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
[src]
Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG4_COUNTER>>
[src]
pub fn init_delay(&self) -> INIT_DELAY_R
[src]
Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
[src]
Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG4_CHAIN_1_0>>
[src]
pub fn csel0(&self) -> CSEL0_R
[src]
Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
[src]
Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
[src]
Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
[src]
Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
[src]
Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
[src]
Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
[src]
Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
[src]
Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG4_CHAIN_3_2>>
[src]
pub fn csel2(&self) -> CSEL2_R
[src]
Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
[src]
Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
[src]
Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
[src]
Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
[src]
Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
[src]
Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
[src]
Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
[src]
Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG4_CHAIN_5_4>>
[src]
pub fn csel4(&self) -> CSEL4_R
[src]
Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
[src]
Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
[src]
Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
[src]
Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
[src]
Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
[src]
Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
[src]
Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
[src]
Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG4_CHAIN_7_6>>
[src]
pub fn csel6(&self) -> CSEL6_R
[src]
Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
[src]
Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG4_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG4_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG4_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG4_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG5_CTRL>>
[src]
pub fn sw_trig(&self) -> SW_TRIG_R
[src]
Bit 0 - Software write 1 as the TRIGGER
pub fn trig_mode(&self) -> TRIG_MODE_R
[src]
Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
[src]
Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
[src]
Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
[src]
Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG5_COUNTER>>
[src]
pub fn init_delay(&self) -> INIT_DELAY_R
[src]
Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
[src]
Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG5_CHAIN_1_0>>
[src]
pub fn csel0(&self) -> CSEL0_R
[src]
Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
[src]
Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
[src]
Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
[src]
Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
[src]
Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
[src]
Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
[src]
Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
[src]
Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG5_CHAIN_3_2>>
[src]
pub fn csel2(&self) -> CSEL2_R
[src]
Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
[src]
Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
[src]
Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
[src]
Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
[src]
Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
[src]
Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
[src]
Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
[src]
Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG5_CHAIN_5_4>>
[src]
pub fn csel4(&self) -> CSEL4_R
[src]
Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
[src]
Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
[src]
Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
[src]
Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
[src]
Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
[src]
Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
[src]
Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
[src]
Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG5_CHAIN_7_6>>
[src]
pub fn csel6(&self) -> CSEL6_R
[src]
Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
[src]
Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG5_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG5_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG5_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG5_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG6_CTRL>>
[src]
pub fn sw_trig(&self) -> SW_TRIG_R
[src]
Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
[src]
Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
[src]
Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
[src]
Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
[src]
Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG6_COUNTER>>
[src]
pub fn init_delay(&self) -> INIT_DELAY_R
[src]
Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
[src]
Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG6_CHAIN_1_0>>
[src]
pub fn csel0(&self) -> CSEL0_R
[src]
Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
[src]
Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
[src]
Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
[src]
Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
[src]
Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
[src]
Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
[src]
Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
[src]
Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG6_CHAIN_3_2>>
[src]
pub fn csel2(&self) -> CSEL2_R
[src]
Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
[src]
Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
[src]
Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
[src]
Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
[src]
Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
[src]
Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
[src]
Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
[src]
Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG6_CHAIN_5_4>>
[src]
pub fn csel4(&self) -> CSEL4_R
[src]
Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
[src]
Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
[src]
Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
[src]
Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
[src]
Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
[src]
Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
[src]
Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
[src]
Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG6_CHAIN_7_6>>
[src]
pub fn csel6(&self) -> CSEL6_R
[src]
Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
[src]
Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG6_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG6_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG6_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG6_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
impl R<u32, Reg<u32, _TRIG7_CTRL>>
[src]
pub fn sw_trig(&self) -> SW_TRIG_R
[src]
Bit 0 - Software write 1 as the TRIGGER. This register is self-clearing.
pub fn trig_mode(&self) -> TRIG_MODE_R
[src]
Bit 4 - TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger.
pub fn trig_chain(&self) -> TRIG_CHAIN_R
[src]
Bits 8:10 - TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8;
pub fn trig_priority(&self) -> TRIG_PRIORITY_R
[src]
Bits 12:14 - External trigger priority, 7 is highest, 0 is lowest .
pub fn sync_mode(&self) -> SYNC_MODE_R
[src]
Bit 16 - TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode
impl R<u32, Reg<u32, _TRIG7_COUNTER>>
[src]
pub fn init_delay(&self) -> INIT_DELAY_R
[src]
Bits 0:15 - TRIGGER initial delay counter
pub fn sample_interval(&self) -> SAMPLE_INTERVAL_R
[src]
Bits 16:31 - TRIGGER sampling interval counter
impl R<u32, Reg<u32, _TRIG7_CHAIN_1_0>>
[src]
pub fn csel0(&self) -> CSEL0_R
[src]
Bits 0:3 - CHAIN0 CSEL ADC channel selection
pub fn hwts0(&self) -> HWTS0_R
[src]
Bits 4:11 - CHAIN0 HWTS ADC hardware trigger selection
pub fn b2b0(&self) -> B2B0_R
[src]
Bit 12 - CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie0(&self) -> IE0_R
[src]
Bits 13:14 - CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
pub fn csel1(&self) -> CSEL1_R
[src]
Bits 16:19 - CHAIN1 CSEL ADC channel selection
pub fn hwts1(&self) -> HWTS1_R
[src]
Bits 20:27 - CHAIN1 HWTS ADC hardware trigger selection
pub fn b2b1(&self) -> B2B1_R
[src]
Bit 28 - CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger
pub fn ie1(&self) -> IE1_R
[src]
Bits 29:30 - CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2
impl R<u32, Reg<u32, _TRIG7_CHAIN_3_2>>
[src]
pub fn csel2(&self) -> CSEL2_R
[src]
Bits 0:3 - CHAIN2 CSEL
pub fn hwts2(&self) -> HWTS2_R
[src]
Bits 4:11 - CHAIN2 HWTS
pub fn b2b2(&self) -> B2B2_R
[src]
Bit 12 - CHAIN2 B2B
pub fn ie2(&self) -> IE2_R
[src]
Bits 13:14 - CHAIN2 IE
pub fn csel3(&self) -> CSEL3_R
[src]
Bits 16:19 - CHAIN3 CSEL
pub fn hwts3(&self) -> HWTS3_R
[src]
Bits 20:27 - CHAIN3 HWTS
pub fn b2b3(&self) -> B2B3_R
[src]
Bit 28 - CHAIN3 B2B
pub fn ie3(&self) -> IE3_R
[src]
Bits 29:30 - CHAIN3 IE
impl R<u32, Reg<u32, _TRIG7_CHAIN_5_4>>
[src]
pub fn csel4(&self) -> CSEL4_R
[src]
Bits 0:3 - CHAIN4 CSEL
pub fn hwts4(&self) -> HWTS4_R
[src]
Bits 4:11 - CHAIN4 HWTS
pub fn b2b4(&self) -> B2B4_R
[src]
Bit 12 - CHAIN4 B2B
pub fn ie4(&self) -> IE4_R
[src]
Bits 13:14 - CHAIN4 IE
pub fn csel5(&self) -> CSEL5_R
[src]
Bits 16:19 - CHAIN5 CSEL
pub fn hwts5(&self) -> HWTS5_R
[src]
Bits 20:27 - CHAIN5 HWTS
pub fn b2b5(&self) -> B2B5_R
[src]
Bit 28 - CHAIN5 B2B
pub fn ie5(&self) -> IE5_R
[src]
Bits 29:30 - CHAIN5 IE
impl R<u32, Reg<u32, _TRIG7_CHAIN_7_6>>
[src]
pub fn csel6(&self) -> CSEL6_R
[src]
Bits 0:3 - CHAIN6 CSEL
pub fn hwts6(&self) -> HWTS6_R
[src]
Bits 4:11 - CHAIN6 HWTS
pub fn b2b6(&self) -> B2B6_R
[src]
Bit 12 - CHAIN6 B2B
pub fn ie6(&self) -> IE6_R
[src]
Bits 13:14 - CHAIN6 IE
pub fn csel7(&self) -> CSEL7_R
[src]
Bits 16:19 - CHAIN7 CSEL
pub fn hwts7(&self) -> HWTS7_R
[src]
Bits 20:27 - CHAIN7 HWTS
pub fn b2b7(&self) -> B2B7_R
[src]
Bit 28 - CHAIN7 B2B
pub fn ie7(&self) -> IE7_R
[src]
Bits 29:30 - CHAIN7 IE
impl R<u32, Reg<u32, _TRIG7_RESULT_1_0>>
[src]
pub fn data0(&self) -> DATA0_R
[src]
Bits 0:11 - Result DATA0
pub fn data1(&self) -> DATA1_R
[src]
Bits 16:27 - Result DATA1
impl R<u32, Reg<u32, _TRIG7_RESULT_3_2>>
[src]
pub fn data2(&self) -> DATA2_R
[src]
Bits 0:11 - Result DATA2
pub fn data3(&self) -> DATA3_R
[src]
Bits 16:27 - Result DATA3
impl R<u32, Reg<u32, _TRIG7_RESULT_5_4>>
[src]
pub fn data4(&self) -> DATA4_R
[src]
Bits 0:11 - Result DATA4
pub fn data5(&self) -> DATA5_R
[src]
Bits 16:27 - Result DATA5
impl R<u32, Reg<u32, _TRIG7_RESULT_7_6>>
[src]
pub fn data6(&self) -> DATA6_R
[src]
Bits 0:11 - Result DATA6
pub fn data7(&self) -> DATA7_R
[src]
Bits 16:27 - Result DATA7
Trait Implementations
Auto Trait Implementations
impl<U, T> Send for R<U, T> where
T: Send,
U: Send,
T: Send,
U: Send,
impl<U, T> Sync for R<U, T> where
T: Sync,
U: Sync,
T: Sync,
U: Sync,
impl<U, T> Unpin for R<U, T> where
T: Unpin,
U: Unpin,
T: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
[src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
[src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]
T: ?Sized,
fn borrow_mut(&mut self) -> &mut T
[src]
impl<T> From<T> for T
[src]
impl<T, U> Into<U> for T where
U: From<T>,
[src]
U: From<T>,
impl<T, U> TryFrom<U> for T where
U: Into<T>,
[src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
[src]
impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
[src]
U: TryFrom<T>,