Type Definition imxrt1062_adc_etc::ctrl::R

type R = R<u32, CTRL>;

Reader of register CTRL

Methods

impl R

pub fn trig_enable(&self) -> TRIG_ENABLE_R

Bits 0:7 - TRIG enable register

pub fn ext0_trig_enable(&self) -> EXT0_TRIG_ENABLE_R

Bit 8 - TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger.

pub fn ext0_trig_priority(&self) -> EXT0_TRIG_PRIORITY_R

Bits 9:11 - External TSC0 trigger priority, 7 is Highest, 0 is lowest .

pub fn ext1_trig_enable(&self) -> EXT1_TRIG_ENABLE_R

Bit 12 - TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger.

pub fn ext1_trig_priority(&self) -> EXT1_TRIG_PRIORITY_R

Bits 13:15 - External TSC1 trigger priority, 7 is Highest, 0 is lowest .

pub fn pre_divider(&self) -> PRE_DIVIDER_R

Bits 16:23 - Pre-divider for trig delay and interval .

pub fn dma_mode_sel(&self) -> DMA_MODE_SEL_R

Bit 29 - 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared

pub fn tsc_bypass(&self) -> TSC_BYPASS_R

Bit 30 - 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared.

pub fn softrst(&self) -> SOFTRST_R

Bit 31 - Software reset, high active. When write 1 ,all logical will be reset.