pub struct Registers {}Expand description
The complete architectural state of the processor.
Every field is public so that a caller restoring a saved machine can write the state directly, which is otherwise awkward to express through accessors. The core reads these fields as it executes, so writing them mid-instruction is permitted but will be observed immediately.
The register pairs are held as 16-bit values with the high byte in the upper half: the high
byte of af is the accumulator and the low byte is the flags.
Fields§
§pc: u16Program counter.
sp: u16Stack pointer.
af: u16Accumulator and flags.
bc: u16The BC pair.
de: u16The DE pair.
hl: u16The HL pair.
af_alt: u16The alternate accumulator and flags, reached with EX AF, AF'.
bc_alt: u16The alternate BC pair, reached with EXX.
de_alt: u16The alternate DE pair, reached with EXX.
hl_alt: u16The alternate HL pair, reached with EXX.
ix: u16The IX index register.
iy: u16The IY index register.
wz: u16The internal address latch, commonly written WZ or MEMPTR.
No instruction reads it directly, but BIT n, (HL) copies two of its bits into the
undocumented flags. That makes it observable, so it’s worth modelling.
i: u8Interrupt vector base, the high byte of the vector address in interrupt mode 2.
r: u8Memory refresh counter. Only the low seven bits count — bit 7 is held across increments.
interrupt_mode: InterruptModeThe selected interrupt mode.
iff1: boolWhether maskable interrupts are currently accepted.
iff2: boolThe copy of iff1 saved when a non-maskable interrupt is accepted. RETN restores it, and
LD A, I or LD A, R make it readable through the parity flag.