Trait SimdArch 

pub trait SimdArch:
    Sealed
    + Send
    + Sync
    + 'static
    + Copy
    + Clone {
    const NAME: &'static str;
    const REGISTER_WIDTH_BITS: u32;
    const ISA_FAMILY: IsaFamily;
    const FMA_THROUGHPUT_HINT: u32;

    // Required method
    fn is_runtime_supported() -> bool;
}

Trait representing a SIMD instruction set architecture.

Implemented by Zero-Sized Types (ZSTs). Constants are queryable without a scalar type parameter — contrast with SimdKernel<T> which requires T to be known.

Required Associated Constants

const NAME: &'static str

Human-readable ISA name ("avx2", "avx512", "neon", "scalar").

const REGISTER_WIDTH_BITS: u32

Width of vector registers in bits.

Architecture	Width
Scalar	0
Neon	128
Avx2	256
Avx512	512

const ISA_FAMILY: IsaFamily

ISA family for this architecture.

const FMA_THROUGHPUT_HINT: u32

Suggested TILE_M value for tiled_dot to saturate FMA throughput.

This is a hint, not a constraint. Optimal values:

• Scalar: 1 (no tiling benefit)
• Neon: 4 (4 NEON regs × 4-cycle FMA latency)
• Avx2: 4 (16 YMM / TILE_M=4 leaves headroom for loop overhead)
• Avx512: 8 (32 ZMM / TILE_M=8 saturates two FMA ports)

Required Methods

fn is_runtime_supported() -> bool

Returns true when the current host may execute this architecture’s native instructions from safe wrappers.

Emulated backends return true; native ISA backends must include the OS-enabled register-state checks covered by the platform feature probe.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementors

impl SimdArch for AmxBf16

const NAME: &'static str = "amx_bf16"

const REGISTER_WIDTH_BITS: u32 = 8192

const ISA_FAMILY: IsaFamily = IsaFamily::X86

const FMA_THROUGHPUT_HINT: u32 = 16

impl SimdArch for AmxInt8

const NAME: &'static str = "amx_int8"

const REGISTER_WIDTH_BITS: u32 = 8192

const ISA_FAMILY: IsaFamily = IsaFamily::X86

const FMA_THROUGHPUT_HINT: u32 = 16

impl SimdArch for Avx2

const NAME: &'static str = "avx2"

const REGISTER_WIDTH_BITS: u32 = 256

const ISA_FAMILY: IsaFamily = hermes_simd_core::arch::IsaFamily::X86

const FMA_THROUGHPUT_HINT: u32 = 4

impl SimdArch for Avx512

const NAME: &'static str = "avx512"

const REGISTER_WIDTH_BITS: u32 = 512

const ISA_FAMILY: IsaFamily = hermes_simd_core::arch::IsaFamily::X86

const FMA_THROUGHPUT_HINT: u32 = 8

impl SimdArch for AvxVnni

const NAME: &'static str = "avx_vnni"

const REGISTER_WIDTH_BITS: u32 = 256

const ISA_FAMILY: IsaFamily = hermes_simd_core::arch::IsaFamily::X86

const FMA_THROUGHPUT_HINT: u32 = 4

impl SimdArch for Neon

const NAME: &'static str = "neon"

const REGISTER_WIDTH_BITS: u32 = 128

const ISA_FAMILY: IsaFamily = hermes_simd_core::arch::IsaFamily::AArch64

const FMA_THROUGHPUT_HINT: u32 = 4

impl SimdArch for Scalar

const NAME: &'static str = "scalar"

const REGISTER_WIDTH_BITS: u32 = 0

const ISA_FAMILY: IsaFamily = hermes_simd_core::arch::IsaFamily::Scalar

const FMA_THROUGHPUT_HINT: u32 = 1

impl SimdArch for SveArch

const NAME: &'static str = "sve-emulated"

const REGISTER_WIDTH_BITS: u32 = 512

const ISA_FAMILY: IsaFamily = IsaFamily::AArch64

const FMA_THROUGHPUT_HINT: u32 = 4