Crate hermes_simd

Expand description

High-performance, zero-overhead SIMD abstraction library.

§Architecture

hermes-simd is the public facade for the hermes-simd workspace:

hermes_simd_core — core abstractions, traits, views
hermes_simd_intrinsics — architecture-specific kernels
hermes_simd_macros — proc-macro code generation

§Feature Flags

Feature	Description
`std` (default)	Runtime CPU feature detection (`is_x86_feature_detected!`); without it dispatch uses compile-time `cfg!(target_feature)` only
`mnemosyne-memory` (default)	Route `AlignedVec` allocation through the mnemosyne allocator
`libnuma`	Linux NUMA affinity and residency probes via libnuma (links `-lnuma`); allocation still routes through Mnemosyne/the configured allocator

§Usage Examples

Dense sum (runtime dispatch):

use hermes_simd::sum;
let data = vec![1.0f32; 1024];
assert_eq!(sum(&data), 1024.0);

Masked dot product:

use hermes_simd::masked_dot;
let a = vec![1.0f32, 2.0, 3.0, 4.0, 5.0];
let b = vec![1.0f32; 5];
let mask = vec![true, false, true, false, true];
assert_eq!(masked_dot(&a, &b, &mask).unwrap(), 9.0); // 1+3+5

Re-exports§

pub use attacks::bishop_attacks;
pub use attacks::queen_attacks;
pub use attacks::rook_attacks;
pub use cpu::has_fma3;
pub use cpu::AmxSupport;
pub use cpu::Avx512Support;
pub use cpu::FmaSupport;
pub use dispatcher::AdaptiveDispatcher;
pub use dispatcher::DispatchDecision;
pub use target::dispatch_view_mut_to;
pub use target::dispatch_view_to;
pub use target::TargetId;
pub use tile_matmul::dispatch_tile_matmul;
pub use tile_matmul::gemm;
pub use tile_matmul::unpack_int4;
pub use tile_matmul::widen_I8_to_I16;
pub use tile_matmul::widen_I8_to_I32;
pub use tile_matmul::widen_i8_to_i16;
pub use tile_matmul::widen_i8_to_i32;
pub use tile_matmul::TiledGemm;
pub use dispatch::abs_max;
pub use dispatch::abs_sum;
pub use dispatch::argmax;
pub use dispatch::argmax;
pub use dispatch::argmin;
pub use dispatch::argmin;
pub use dispatch::axpy;
pub use dispatch::axpy_mul;
pub use dispatch::axpy_rows;
pub use dispatch::axpy_rows_batch;
pub use dispatch::dot;
pub use dispatch::dot;
pub use dispatch::elementwise_add;
pub use dispatch::elementwise_div;
pub use dispatch::elementwise_mul;
pub use dispatch::elementwise_sub;
pub use dispatch::gemv;
pub use dispatch::gemv;
pub use dispatch::gemv_strided;
pub use dispatch::gemv_strided;
pub use dispatch::gemv_transpose;
pub use dispatch::gemv_transpose;
pub use dispatch::gemv_transpose_strided;
pub use dispatch::gemv_transpose_strided;
pub use dispatch::interleaved_complex_dot;
pub use dispatch::interleaved_complex_dot_runtime;
pub use dispatch::interleaved_complex_mul_assign;
pub use dispatch::interleaved_complex_mul_assign_runtime;
pub use dispatch::masked_add;
pub use dispatch::masked_dot;
pub use dispatch::masked_sum;
pub use dispatch::max;
pub use dispatch::max;
pub use dispatch::min;
pub use dispatch::min;
pub use dispatch::ntt_butterfly_stage_u64;
pub use dispatch::reduce_popcount;
pub use dispatch::reduce_popcount_and;
pub use dispatch::reduce_popcount_or;
pub use dispatch::reduce_popcount_xor;
pub use dispatch::scale;
pub use dispatch::scale;
pub use dispatch::spmv_bcoo;
pub use dispatch::spmv_csr;
pub use dispatch::spmv_dense_masked;
pub use dispatch::spmv_sellp;
pub use dispatch::sum;
pub use dispatch::sum;
pub use dispatch::tiled_gemm;
pub use dispatch::SimdOps;

Modules§

attacks: Chess board attack generation kernels using bitboards and SWAR.
cpu: Runtime CPU feature detection utilities.
dispatch: Runtime-dispatched SIMD abstractions and dynamic facade. Runtime-dispatched SIMD operations.
dispatcher: Dynamic dispatcher choosing optimal backends based on hardware/layout. Dynamic runtime dispatch choosing the optimal execution backend.
target: Explicit runtime target tokens and forced dispatch helpers. Explicit SIMD target tokens and forced view dispatch helpers.
tile_matmul: Tiled matrix multiplication dispatch and kernel interfaces. Register-blocked tile matrix multiplication module.

Structs§

Abs: Elementwise absolute value: |a[i]|.
Add: Elementwise addition: a[i] + b[i].
Aligned: A static alignment guarantee of A bytes.
AlignedVec: A heap-allocated vector with statically guaranteed memory alignment layout.
AmxBatchSession: An RAII guard that encapsulates a complete AMX batch computation.
AmxBf16: x86/x86_64 AMX BF16 matrix multiply backend.
AmxConfig: 64-byte AMX tile configuration structure (TILECFG).
AmxInt8: x86/x86_64 AMX INT8 matrix multiply backend.
AmxSession: A session guard that manages AMX tile configuration lifecycle on the current thread.
ArchivedPacked4Cow: Archived representation of a Packed4Cow for zero-copy deserialization.
ArchivedSimdCow: Archived representation of a SimdCow used by rkyv zero-copy serialization.
Avx2: x86/x86_64 AVX2 instruction set architecture marker.
Avx512: x86/x86_64 AVX-512F instruction set architecture marker.
AvxVnni: x86/x86_64 AVX-VNNI (256-bit VEX-encoded VNNI) instruction set marker.
Bf4: Brain Float 4: finite-only E2M1 with the top exponent reserved for NaN.
Bf8: Brain Float 8: IEEE-style E5M2 with infinity and NaN.
Bf16: bfloat16 (E8M7), stored as its raw u16 bit pattern.
BitAnd: Elementwise bitwise AND: a[i] & b[i].
BitBoardView: A zero-copy newtype family for chess bitboards.
BitMask: Bit-packed predicate mask for exactly N SIMD lanes.
BitOr: Elementwise bitwise OR: a[i] | b[i].
BitXor: Elementwise bitwise XOR: a[i] ^ b[i].
BlockedCoo: Blocked COO format marker.
Clamp: Elementwise clamp: min(max(a[i], lo), hi).
ColMajor: Column-major (Fortran-order) layout marker ZST.
Csr: Compressed Sparse Row format marker.
DenseWithMask: Dense storage with a boolean mask indicating non-zero elements.
Div: Elementwise division: a[i] / b[i].
Dot: Dot-product pairwise operation: multiply two vectors lane-wise.
Exclusive: Exclusive scan ZST marker.
F4: Finite-only 4-bit float: E3M0 with the top exponent reserved for NaN.
F8: Finite-only 8-bit float: E4M3 with the top exponent reserved for NaN.
F16: IEEE 754 binary16 (half precision), stored as its raw u16 bit pattern.
F32: Transparent wrapper for f32.
F64: Transparent wrapper for f64.
FmaAdd: Fused-multiply-add elementwise operation: out[i] = a[i] * b[i] + a[i] (binary form).
HybridSwarMagic: ZST marker for hybrid SWAR and Magic Bitboards backend.
Hyperbola: ZST marker for Hyperbola Quintessence backend.
I8: Transparent wrapper for i8.
I16: Transparent wrapper for i16.
I32: Transparent wrapper for i32.
Inclusive: Inclusive scan ZST marker.
KoggeStone: ZST marker for direction-parallel vectorized Kogge-Stone backend.
Magic: ZST marker for Fancy Magic Bitboards backend.
Mask: A type-safe, architecture-native SIMD mask type.
Masked: Predicated execution — a hardware mask selects active lanes.
Mul: Elementwise multiplication: a[i] * b[i].
Neg: Elementwise negation: -a[i].
Neon: AArch64 NEON instruction set architecture marker.
NumaBinding: RAII scope guard that binds the current thread to a specific NUMA node.
OwnedBlockedCoo: Owned heap-backed Blocked-COO storage.
OwnedCsr: Owned heap-backed CSR storage.
OwnedDenseWithMask: Owned heap-backed DenseWithMask storage.
OwnedSellP: Owned heap-backed SELL-p storage.
Packed4CowResolver: Resolver type for Packed4Cow.
Packed4Iter: Iterator over a packed 4-bit slice.
Packed4Slice: A read-only view over a packed slice of 4-bit values, stored 2 per byte.
Packed4SliceMut: A mutable view over a packed slice of 4-bit values, stored 2 per byte.
Packed4Vec: A heap-allocated packed vector of 4-bit values, stored 2 per byte.
Popcount: Elementwise population count: count of set bits in each lane.
Product: Multiplicative reduction: computes ∏ data[i].
RecipSqrt: Elementwise reciprocal square root: 1.0 / sqrt(a[i]).
RowMajor: Row-major (C-order) layout marker ZST.
Scalar: Fallback scalar implementation marker.
ScanAdd: Addition scan strategy ZST marker.
ScanMax: Maximum scan strategy ZST marker.
ScanMin: Minimum scan strategy ZST marker.
ScanMul: Multiplication scan strategy ZST marker.
SellP: Sliced ELLPACK format marker.
SimdChunks: Iterator over non-overlapping LANE_COUNT-wide sub-views of a SimdView.
SimdChunksMut: Iterator over non-overlapping mutable LANE_COUNT-wide sub-views of a SimdView.
SimdCowResolver: Resolver type for SimdCow serialization.
SimdView: A zero-copy, typed slice view parameterized by architecture, alignment, execution mode, and reference typestates.
SparseView: Format-parameterized sparse matrix view.
Sqrt: Elementwise square root: sqrt(a[i]).
Sub: Elementwise subtraction: a[i] - b[i].
Sum: Sum reduction: accumulate by adding vectors, finalize with sum_reduce.
SveArch: AArch64 SVE architecture ZST marker.
Swar: ZST marker for pure SWAR primitives backend.
SwarUtils: Pure SWAR bitwise utility primitives.
TensorView: Zero-copy N-dimensional strided view over a borrowed slice.
TileView: A 2D matrix tile view, parameterized by dimensions, alignment, execution mode, and backing reference type.
TilingPolicy: Zero-sized strategy marker for tiled execution policy.
Unaligned: No static alignment guarantee.
Unmasked: Dense execution — all lanes are active. Default mode for crate::view::SimdView.
Validated: Typestate marker for sparse formats whose structural invariants were checked before kernel entry.
ValidatedData: Sparse storage whose structural invariants have been checked once at construction.
Vector: A monomorphized vector register type wrapping the architecture-native raw register.
ZipChunks: Iterator over non-overlapping paired LANE_COUNT-wide sub-views of two SimdViews.
ZipChunksMut: Paired iterator over non-overlapping LANE_COUNT-wide sub-views where the first operand is mutable and the second is immutable.

Enums§

AmxSessionError: Error returned when an AMX session cannot be entered safely.
DispatchedView: Target-specific, runtime-dispatched SIMD view wrapper.
Packed4Cow: A Clone-on-Write (CoW) container for packed 4-bit elements.
SimdCow: A Clone-on-Write SIMD container.
SimdError: Error types for SIMD view operations.
SparseCow: Clone-on-Write sparse matrix, generic over the storage format F.
TensorCow: A Clone-on-Write (CoW) container for strided tensors.
TensorError: Error type for tensor construction and indexing.

Traits§

Alignment: Trait representing a memory alignment guarantee.
BitBoardKernel: Trait defining the sliding attack generation interface.
CastFrom: Helper trait for generic casting between SIMD scalar types.
CastTo: Helper trait for generic casting to another SIMD scalar type.
ComputeReduce: Extension trait that provides reduce() over any SimdView-backed ComputeView.
ComputeView: Top-level trait abstracting over dense, masked, sparse, tiled, and bitboard backends.
CowFormat: Maps a sparse format marker to its owned storage and Cow conversions.
ElementOp: Sealed ZST trait for pairwise SIMD elementwise operations.
ExecutionMode: Marker trait for SIMD execution modes.
FloatElement: Float-specific capabilities.
Packable4: Trait for 4-bit types that can be packed two per byte.
Packed4CowExt: Extension trait for packed Clone-on-Write containers to support zero-copy unpacking directly into SimdCow.
ReductionOp: Sealed ZST trait for SIMD horizontal reduction strategies.
ScanMode: Sealed ZST trait for prefix scan inclusion modes.
ScanOp: Sealed ZST trait for prefix scan operations.
SimdArch: Trait representing a SIMD instruction set architecture.
SimdCowExt: Extension trait for SimdCow providing vector-register level operations.
SimdKernel: Abstract trait defining low-level vector operations.
SimdScalar: Core numeric element trait. The main extension point for monomorphized operations across all precisions.
SparseFormat: Marker trait for sparse matrix storage formats.
SparseOps: Unified trait for elementwise and reduction operations on sparse matrices.
SparseSpMv: Unified trait for sparse matrix-vector multiplication.
TileMatrixMultiply: Trait mediating zero-overhead matrix multiplication on 2D tiles.
TilingStrategy: Trait representing a monomorphized register-blocking/tiling strategy.
UnaryOp: Sealed ZST trait for single-operand SIMD elementwise operations.

Functions§

current_numa_node: Returns the index of the NUMA node the current thread is executing on.
dispatch_view: Dispatches a shared slice into the best matching DispatchedView based on runtime CPU feature detection.
dispatch_view_mut: Dispatches a mutable slice into the best matching DispatchedView based on runtime CPU feature detection.
refresh_numa_node: Refreshes and returns the current NUMA node index for the executing thread.
tiled_dot: Compute the dot product of two slices using TILE_M independent vector accumulators.
tiled_gemv: Compute a register-blocked tiled GEMV: y += A * x.
unpack_bf4_to_bf16: Unpacks Bf4 elements to Bf16.
unpack_bf4_to_bf16_packed: Unpacks packed 4-bit Bf4 pairs (stored 2 per byte) into a Bf16 slice.
unpack_bf8_to_bf16: Unpacks Bf8 elements to Bf16.
unpack_f4_to_f32: Unpacks F4 elements to F32.
unpack_f4_to_f32_packed: Unpacks packed 4-bit F4 pairs (stored 2 per byte) into an F32 slice.
unpack_f8_to_f32: Unpacks F8 elements to F32.
verify_numa_locality: Verify if the physical memory backing a pointer range is resident on a specific node.

Type Aliases§

Avx2Bf4: Concrete AVX2 bfloat4 vector register (32 lanes).
Avx2Bf8: Concrete AVX2 bfloat8 vector register (32 lanes).
Avx2Bf16: Concrete AVX2 bfloat16 vector register (16 lanes).
Avx2F4: Concrete AVX2 float4 vector register (32 lanes).
Avx2F8: Concrete AVX2 float8 vector register (32 lanes).
Avx2F16: Concrete AVX2 standard f16 vector register (16 lanes).
Avx2F32: Concrete AVX2 f32 vector register (8 lanes).
Avx2F64: Concrete AVX2 f64 vector register (4 lanes).
Avx2I8: Concrete AVX2 i8 vector register (32 lanes).
Avx2I16: Concrete AVX2 i16 vector register (16 lanes).
Avx2I32: Concrete AVX2 i32 vector register (8 lanes).
Avx2MaskBf16: Concrete AVX2 bfloat16 mask register (16 lanes).
Avx2MaskF16: Concrete AVX2 f16 mask register (16 lanes).
Avx2MaskF32: Concrete AVX2 f32 mask register (8 lanes).
Avx2MaskF64: Concrete AVX2 f64 mask register (4 lanes).
Avx512Bf4: Concrete AVX-512 bfloat4 vector register (64 lanes).
Avx512Bf8: Concrete AVX-512 bfloat8 vector register (64 lanes).
Avx512Bf16: Concrete AVX-512 bfloat16 vector register (32 lanes).
Avx512F4: Concrete AVX-512 float4 vector register (64 lanes).
Avx512F8: Concrete AVX-512 float8 vector register (64 lanes).
Avx512F16: Concrete AVX-512 standard f16 vector register (32 lanes).
Avx512F32: Concrete AVX-512 f32 vector register (16 lanes).
Avx512F64: Concrete AVX-512 f64 vector register (8 lanes).
Avx512I8: Concrete AVX-512 i8 vector register (64 lanes).
Avx512I16: Concrete AVX-512 i16 vector register (32 lanes).
Avx512I32: Concrete AVX-512 i32 vector register (16 lanes).
Avx512MaskBf16: Concrete AVX-512 bfloat16 mask register (32 lanes).
Avx512MaskF16: Concrete AVX-512 f16 mask register (32 lanes).
Avx512MaskF32: Concrete AVX-512 f32 mask register (16 lanes).
Avx512MaskF64: Concrete AVX-512 f64 mask register (8 lanes).
BlockedCooData: Backward-compatible type alias.
CsrData: Backward-compatible type alias.
DenseWithMaskData: Backward-compatible type alias.
MaskBf4: Generic bfloat4 SIMD lane selection mask.
MaskBf8: Generic bfloat8 SIMD lane selection mask.
MaskBf16: Generic bfloat16 SIMD lane selection mask.
MaskF4: Generic float4 SIMD lane selection mask.
MaskF8: Generic float8 SIMD lane selection mask.
MaskF16: Generic standard f16 SIMD lane selection mask.
MaskF32: Generic f32 SIMD lane selection mask.
MaskF64: Generic f64 SIMD lane selection mask.
MaskI8: Generic i8 SIMD lane selection mask.
MaskI16: Generic i16 SIMD lane selection mask.
MaskI32: Generic i32 SIMD lane selection mask.
PackedBf4Cow: Type alias for a Clone-on-Write view over packed Bf4 values.
PackedBf4Slice: Type alias for a read-only view over a packed slice of Bf4 values.
PackedBf4SliceMut: Type alias for a mutable view over a packed slice of Bf4 values.
PackedBf4Vec: Type alias for a heap-allocated packed vector of Bf4 values.
PackedF4Cow: Type alias for a Clone-on-Write view over packed F4 values.
PackedF4Slice: Type alias for a read-only view over a packed slice of F4 values.
PackedF4SliceMut: Type alias for a mutable view over a packed slice of F4 values.
PackedF4Vec: Type alias for a heap-allocated packed vector of F4 values.
PreferredArch: The optimal target architecture typestate compiled for the current host CPU target.
ScalarBf4: Concrete 1-element scalar emulation bfloat4 vector register.
ScalarBf8: Concrete 1-element scalar emulation bfloat8 vector register.
ScalarBf16: Concrete 1-element scalar emulation bfloat16 vector register.
ScalarF4: Concrete 1-element scalar emulation float4 vector register.
ScalarF8: Concrete 1-element scalar emulation float8 vector register.
ScalarF16: Concrete 1-element scalar emulation f16 vector register.
ScalarF32: Concrete 1-element scalar emulation f32 vector register.
ScalarF64: Concrete 1-element scalar emulation f64 vector register.
ScalarI8: Concrete 1-element scalar emulation i8 vector register.
ScalarI16: Concrete 1-element scalar emulation i16 vector register.
ScalarI32: Concrete 1-element scalar emulation i32 vector register.
ScalarMaskF32: Concrete 1-element scalar emulation f32 mask register.
ScalarMaskF64: Concrete 1-element scalar emulation f64 mask register.
SellPData: Backward-compatible type alias.
SimdBf4: Optimal bfloat4 SIMD register compiled for the host.
SimdBf8: Optimal bfloat8 SIMD register compiled for the host.
SimdBf16: Optimal bfloat16 SIMD register compiled for the host.
SimdF4: Optimal float4 SIMD register compiled for the host.
SimdF8: Optimal float8 SIMD register compiled for the host.
SimdF16: Optimal f16 SIMD register compiled for the host.
SimdF32: Optimal f32 SIMD register compiled for the host.
SimdF64: Optimal f64 SIMD register compiled for the host.
SimdI8: Optimal i8 SIMD register compiled for the host.
SimdI16: Optimal i16 SIMD register compiled for the host.
SimdI32: Optimal i32 SIMD register compiled for the host.
SimdMaskBf4: Optimal bfloat4 SIMD mask register compiled for the host.
SimdMaskBf8: Optimal bfloat8 SIMD mask register compiled for the host.
SimdMaskBf16: Optimal bfloat16 SIMD mask register compiled for the host.
SimdMaskF4: Optimal float4 SIMD mask register compiled for the host.
SimdMaskF8: Optimal float8 SIMD mask register compiled for the host.
SimdMaskF16: Optimal f16 SIMD mask register compiled for the host.
SimdMaskF32: Optimal f32 SIMD mask register compiled for the host.
SimdMaskF64: Optimal f64 SIMD mask register compiled for the host.
SimdMaskI8: Optimal i8 SIMD mask register compiled for the host.
SimdMaskI16: Optimal i16 SIMD mask register compiled for the host.
SimdMaskI32: Optimal i32 SIMD mask register compiled for the host.
VectorBf4: Generic bfloat4 SIMD vector register.
VectorBf8: Generic bfloat8 SIMD vector register.
VectorBf16: Generic bfloat16 SIMD vector register.
VectorF4: Generic float4 SIMD vector register.
VectorF8: Generic float8 SIMD vector register.
VectorF16: Generic standard f16 SIMD vector register.
VectorF32: Generic f32 SIMD vector register.
VectorF64: Generic f64 SIMD vector register.
VectorI8: Generic i8 SIMD vector register.
VectorI16: Generic i16 SIMD vector register.
VectorI32: Generic i32 SIMD vector register.

Crate hermes_simd

Crate hermes_simd Copy item path

§Architecture

§Feature Flags

§Usage Examples

Re-exports§

Modules§

Structs§

Enums§

Traits§

Functions§

Type Aliases§

Crate hermes_simd