Struct SimulatorBuilder

pub struct SimulatorBuilder { /* private fields */ }

Builds a simulator

See crate level documentation for a usage example

Implementations

impl SimulatorBuilder

pub fn iter_wire_ids(&self) -> impl Iterator<Item = WireId> + '_

Iterates over all wire IDs in the graph

pub fn iter_component_ids(&self) -> impl Iterator<Item = ComponentId> + '_

Iterates over all component IDs in the graph

pub fn get_wire_width( &self, wire: WireId, ) -> Result<NonZeroU8, InvalidWireIdError>

Gets the width of a wire

pub fn set_wire_drive( &mut self, wire: WireId, new_drive: &LogicState, ) -> Result<(), InvalidWireIdError>

Drives a wire to a certain state without needing a component

Any unspecified bits will be set to Z

pub fn get_wire_drive( &self, wire: WireId, ) -> Result<LogicState, InvalidWireIdError>

Gets the current drive of a wire

pub fn get_component_data( &self, component: ComponentId, ) -> Result<ComponentData<'_, Immutable>, InvalidComponentIdError>

Gets a components data

pub fn get_component_data_mut( &mut self, component: ComponentId, ) -> Result<ComponentData<'_, Mutable>, InvalidComponentIdError>

Gets a components data mutably

pub fn set_wire_name<S: Into<Arc<str>>>( &mut self, wire: WireId, name: S, ) -> Result<(), InvalidWireIdError>

Assigns a name to a wire

pub fn get_wire_name( &self, wire: WireId, ) -> Result<Option<&str>, InvalidWireIdError>

Gets the name of a wire, if one has been assigned

pub fn set_component_name<S: Into<Arc<str>>>( &mut self, component: ComponentId, name: S, ) -> Result<(), InvalidComponentIdError>

Assigns a name to a component

pub fn get_component_name( &self, component: ComponentId, ) -> Result<Option<&str>, InvalidComponentIdError>

Gets the name of a component, if one has been assigned

pub fn stats(&self) -> SimulationStats

Collects statistics of the simulation

pub fn write_dot<W: Write>(&self, writer: W) -> Result<()>

Writes the simulation graph into a Graphviz DOT file

impl SimulatorBuilder

pub fn add_wire(&mut self, width: NonZeroU8) -> Option<WireId>

Adds a wire to the simulation

Returns None if the memory limit for wires has been reached

pub fn add_and_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds an AND Gate component to the simulation

pub fn add_or_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds an OR Gate component to the simulation

pub fn add_xor_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds an XOR Gate component to the simulation

pub fn add_nand_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds a NAND Gate component to the simulation

pub fn add_nor_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds a NOR Gate component to the simulation

pub fn add_xnor_gate( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds an XNOR Gate component to the simulation

pub fn add_add( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds an ADD component to the simulation

pub fn add_sub( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a SUB component to the simulation

pub fn add_mul( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a MUL component to the simulation

pub fn add_left_shift( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a Left Shift component to the simulation

pub fn add_logical_right_shift( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a Logical Right Shift component to the simulation

pub fn add_arithmetic_right_shift( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds an Arithmetic Right Shift component to the simulation

pub fn add_not_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a NOT Gate component to the simulation

pub fn add_neg(&mut self, input: WireId, output: WireId) -> AddComponentResult

Adds a NEG component to the simulation

pub fn add_buffer( &mut self, input: WireId, enable: WireId, output: WireId, ) -> AddComponentResult

Adds a Buffer component to the simulation

pub fn add_slice( &mut self, input: WireId, offset: u8, output: WireId, ) -> AddComponentResult

Adds a Slice component to the simulation

pub fn add_merge( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds a Merge component to the simulation

pub fn add_adder( &mut self, input_a: WireId, input_b: WireId, carry_in: WireId, output: WireId, carry_out: WireId, ) -> AddComponentResult

Adds an Adder component to the simulation

pub fn add_multiplexer( &mut self, inputs: &[WireId], select: WireId, output: WireId, ) -> AddComponentResult

Adds a Multiplexer component to the simulation

pub fn add_priority_decoder( &mut self, inputs: &[WireId], output: WireId, ) -> AddComponentResult

Adds a Priority Decoder component to the simulation

pub fn add_register( &mut self, data_in: WireId, data_out: WireId, enable: WireId, clock: WireId, clock_polarity: ClockPolarity, ) -> AddComponentResult

Adds a Register component to the simulation

pub fn add_horizontal_and_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal AND Gate component to the simulation

pub fn add_horizontal_or_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal OR Gate component to the simulation

pub fn add_horizontal_xor_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal XOR Gate component to the simulation

pub fn add_horizontal_nand_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal NAND Gate component to the simulation

pub fn add_horizontal_nor_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal NOR Gate component to the simulation

pub fn add_horizontal_xnor_gate( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a Horizontal XNOR Gate component to the simulation

pub fn add_compare_equal( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds an equality comparator component to the simulation

pub fn add_compare_not_equal( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds an inequality comparator component to the simulation

pub fn add_compare_less_than( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘less than’ comparator component to the simulation

pub fn add_compare_greater_than( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘greater than’ comparator component to the simulation

pub fn add_compare_less_than_or_equal( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘less than or equal’ comparator component to the simulation

pub fn add_compare_greater_than_or_equal( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘greater than or equal’ comparator component to the simulation

pub fn add_compare_less_than_signed( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘signed less than’ comparator component to the simulation

pub fn add_compare_greater_than_signed( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘signed greater than’ comparator component to the simulation

pub fn add_compare_less_than_or_equal_signed( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘signed less than or equal’ comparator component to the simulation

pub fn add_compare_greater_than_or_equal_signed( &mut self, input_a: WireId, input_b: WireId, output: WireId, ) -> AddComponentResult

Adds a ‘signed greater than or equal’ comparator component to the simulation

pub fn add_zero_extend( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a zero extension component to the simulation

pub fn add_sign_extend( &mut self, input: WireId, output: WireId, ) -> AddComponentResult

Adds a sign extension component to the simulation

pub fn add_ram( &mut self, write_addr: WireId, data_in: WireId, read_addr: WireId, data_out: WireId, write: WireId, clock: WireId, clock_polarity: ClockPolarity, ) -> AddComponentResult

Adds a RAM component to the simulation

pub fn add_rom(&mut self, addr: WireId, data: WireId) -> AddComponentResult

Adds a ROM component to the simulation

pub fn import_module<T: ModuleImporter>( &mut self, importer: &T, ) -> Result<ModuleConnections, T::Error>

Imports a module into this circuit

pub fn build(self) -> Simulator

Creates the simulator

impl SimulatorBuilder

pub fn build_with_trace<VCD: Write>( self, vcd: VCD, timescale: Timescale, ) -> Result<Simulator<VCD>>

Creates the simulator and attaches VCD tracing

Trait Implementations

impl Default for SimulatorBuilder

fn default() -> Self

Returns the “default value” for a type.